MOSFET Degradation Research Articles

Eliminating Repetitive Short-Circuit Degradation and Failure of 1.2-kV SiC Power MOSFETs

Silicon carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short-circuit (SC) stress. In this article, a new approach, named Baliga Short-Circuit Improvement Concept (BaSIC) depletion-mode MOSFET (DMM), is demonstrated to prevent the degradation and failure of 1.2-kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate–source-shorted Si DMM connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.

Investigation of the Temperature Dependence of Hot-Carrier Degradation in Si MOSFETs Using Spectroscopic Charge Pumping

The temperature dependence of defect generation due to hot-carrier stress (HCS) is investigated in long-channel nMOSFETs with a SiO2 insulator. In order to improve the understanding of hot-carrier degradation, we systematically investigate the impact of temperature on the HCS-induced trap densities and their energetic profiles using standard and spectroscopic charge pumping (CP). With the aid of polyheaters, which can rapidly change the device temperature, recovery of the degradation at higher temperatures is minimized by quickly switching the temperature to the characterization temperature of −60 °C. In order to be able to quantitatively analyze the trap profiles measured with spectroscopic CP, a method for finding the correct capture cross section is suggested. Both CP methods yield comparable results, and it is shown that the same types of defects are created at all temperatures. In agreement with the literature, lower stress temperatures during HCS result in the creation of a larger number of defects for our long-channel devices.

Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing (SS) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS. Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor.

A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part II: Technology Scaling

Transistor parametric drift due to conduction mode hot carrier degradation (HCD) is reviewed. The time kinetics in n-channel MOSFETs and FinFETs is analyzed for channel length ( ${L}_{\text {CH}}$ ) variation from $\sim 2~\mu \text{m}$ to ~20 nm and oxide thickness ( ${T}_{\text {OX}}$ ) scaling from ~20 to ~1 nm, for drain bias ( ${V}_{\text {D}}$ ) variation from ~8 to ~1 V, and gate bias ( ${V}_{\text {G}}$ ) chosen to achieve a maximum HCD for a particular type of device. The time kinetics shape variation from long-channel heavily doped abrupt junction devices through moderately long-channel lightly doped drain (LDD) devices to short-channel devices featuring moderately doped source–drain extensions (SDEs) is reviewed. The temperature ( ${T}$ ) dependence of HCD and the comparison of dc and ac HCD stress kinetics are reviewed in long ${L}_{\text {CH}}$ at high ${V}_{\text {D}}$ and in short ${L}_{\text {CH}}$ at low ${V}_{\text {D}}$ stress. The observed data are qualitatively explained.

A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part I: Physical Mechanism

Transistor parametric drift due to conduction-mode hot carrier degradation (HCD) in n-MOSFETs is reviewed, for long- and short-channel length ( ${L}_{\text {CH}}{)}$ devices having different source/drain (S/D) junction structures. The HCD magnitude and time kinetics shape are discussed for stress under different gate ( ${V}_{\text {G}}{)}$ and drain ( ${V}_{\text {D}}{)}$ biases with varying ${V}_{\text {G}}/{V}_{\text {D}}$ ratio, and without and with substrate bias ( ${V}_{\text {B}}{)}$ . Post-dc stress kinetics is discussed. The published data are qualitatively analyzed to identify the roles of different underlying physical mechanisms. In part II of this article, impacts of technology scaling and stress temperature (T) and comparison of dc and ac stress are discussed.

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.

A Practical On-Board SiC MOSFET Condition Monitoring Technique for Aging Detection

In this article, an in situ SiC mosfet degradation monitoring method using readily available converter sensors is presented. Device's drain-source resistance in saturation and ohmic regions are employed as aging precursors to, respectively, indicate die and package-related degradations. The presented findings in this article are essential for low-cost and practical early warning systems in power electronics applications. To verify the effectiveness of the proposed method, a number of power-cycling tests are conducted to analyze aging process and fatigue mechanism. Device static parameters are measured throughout accelerated aging tests and the physical causes behind them are discussed in detail. It is shown that the drain-source resistance within saturation region at low gate bias can be used to indicate die-related degradation. Similarly, at full positive gate bias, device on-state drain-source resistance can be used to detect package-related degradation. In order to find out optimal variables such as applied gate bias, pulse duration, etc., a comprehensive single pulse test is conducted and the results are reported. Finally, the proposed degradation monitoring method is experimentally validated in the context of a three-phase inverter considering different sensor configurations and load types.

Investigation on Degradation of SiC MOSFET Under Accelerated Stress in a PFC Converter

The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this article, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2-kW power factor correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional dc power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in a PFC converter. Online monitoring results show that the ON-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in ON-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain-source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation, and C- V measurement indicate that the main degradation mechanism is hot holes accumulation within the gate oxide above the JFET region and channel region due to high electric field stress.

Extraction of Series Resistance and Mobility Degradation in MOSFETs Using Iterative Method

Series resistance and mobility attenuation parameter are parasitic phenomena that limit the scaling of advanced MOSFETs. In this work, an iterative method is proposed to extract the series resistance and mobility degradation parameter in short channel MOSFETs. It also allows us to extract the surface roughness amplitude. The principle of this method is based on the exponential model of effective mobility and the least squares methods. From these, two analytical equations are obtained to determine the series resistance and the low field mobility as function of the mobility degradation. The mobility attenuation parameter is extracted using an iterative procedure to minimize the root means squared error (RMSE) value. The results obtained by this technique for a single short channel device have shown the good agreement with measurements data at strong inversion. 

Investigation of Hot-Carrier Degradation in 0.18-$\mu$ m MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

In this work, we investigate the hot-carrier reliability in $0.18{\mu}\text{m}$ MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs = Vds/2 and maximum hot-electron injection condition Vgs = Vds . Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.

Channel-length dependence of mechanical stress effect by hybrid shallow trench isolation on NBTI degradation of HfSiON/SiO2p-channel MOSFETs with strained Si/SiGe channel

This paper quantifies how mechanical stress induced by the hybrid shallow trench isolation affects negative bias temperature instability (NBTI) degradation of p-type channel MOSFETs (pMOSFETs) that have a strained Si/SiGe channel. As the channel length L decreased, the NBTI degradation decreased and electrical characteristics degraded. Experimental results indicate that tensile stress σt applied to the channel region decreased the energy band-gap by increasing the intrinsic carrier concentration. NBTI degradation was not affected by application of an oxide electric field to compensate for the charge that is induced differently in the Si channel during strong inversion. The distribution of the shift ΔVth of threshold voltage before and after NBTI stress in the channel region was also examined. As L decreased, the decrease of ΔVth was greater in the gate edge region than in the center region. These results show that the observed L-dependence of NBTI degradation characteristics were caused by σt in the channel region, and affected the gate edge region dominantly. Therefore, to achieve reliable high-k pMOSFETs with the strained Si/SiGe channel as L is scaled down, methods should be developed to control mechanical stress in the gate edge region.

Reliability evaluation of power MOSFETs used for an initial charge method using multiple short-circuits in each leg

This paper evaluates the power device reliability under the initial charge method which makes multiple short-circuits one after the other to suppress overvoltage. The initial charge method using multiple short-circuits is tested more than 10,000 cycles on the practical power converter. The experimental results exhibit that the cycle number until the on-resistance changes by 20% is increased from 200 to more than 10,000 by the multiple short-circuits. As a result, the multiple short-circuits can reduce degradation of MOSFETs and increase the lifetime of power converter.

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.

High-Source–Drain Voltage-Induced Reliability Issues of Sub-28-nm Node MOSFET’s Application in Resistive-Type Nonvolatile Memory Array

In this brief, we investigate the reliability issues of MOSFETs with bulk 28-nm technology for its possible application in resistive-type nonvolatile memory (RNVM). The impact of electrical stress on transistors when working in the 1T1R array cells is discussed. It is found that the high source-drain voltage bias during the 1T1R array operation is the main reason causing the MOSFET degradation. Furthermore, by comparing the electrical characteristics of MOSFETs with different channel lengths, it is confirmed that the degradation is caused by high-energy electrons drifting from the source side to the drain end under a high electric field. As a result, this issue will be more serious as the gate length continues to scale down. An ultralow operation voltage RNVM is required for a better lifetime if RNVM is embedded in sub-28-nm technologies.

The impact of reactor neutron irradiation on total ionizing dose degradation in MOSFET

Three kinds of MOSFETs with thick oxide layer and long channel were designed to do experiments and analysis on the impact of reactor neutron irradiation on total ionizing dose (TID) degradation in MOSFET. The individual gamma irradiation and the sequential irradiation of reactor neutrons and gamma rays were accomplished on the transistors. The results demonstrate that reactor neutron irradiation enhanced subsequent TID degradation in MOSFET, which was further analysed by Geant4 simulation. Neutron irradiation can also induce total ionizing dose effects rather than displacement effects in MOSFETs. The mechanism of the enhanced degradation under the sequential neutron and gamma irradiation is that ionizing energy loss by incident neutrons also makes ionizing dose accumulation in MOSFET, and neutron-induced and gamma-induced TID degradation are added together, leading to more severe degradation than that under the individual gamma irradiation.

Sub-nanometer-scale depth profiling of nitrogen atoms in SiO2/4H-SiC structures treated with NO annealing

We developed a technique to probe, with sub-nanometer-scale resolution, depth profiles of nitrogen atoms in NO-treated SiO2/4H-SiC structures for Si- and C-face substrates. This technique revealed that preferential nitridation only at the SiO2/SiC interfaces proceeds in the initial stage of NO annealing. Then, for the Si-face, a longer NO treatment leads to a nitrogen distribution in SiO2 within a few nm of the interface. This result is in line with the mobility degradation in MOSFETs subjected to excessive NO annealing. For the C-face, a larger amount of nitrogen was introduced and the depth profile was unchanged after reaching a saturation level.

Method to estimate profile of threshold voltage degradation in MOSFETs due to electrical stress

This paper presents a method to measure the threshold voltage degradation ΔVth along the channel direction due to electrical stress in MOSFETs. This method uses ΔVths measured after electrical stress at different drain bias Vds, and calculated the depletion length Ldep into the channel for each condition under which ΔVth is measured. By substituting ΔVth and Ldep into the proposed equation, the amount of degradation generated in each region of the MOSFET channel can be calculated. The ΔVth profiles of OFF-state stress and negative bias temperature instability in pMOSFET and hot carrier injection in nMOSFET were extracted using the proposed method. The degradation profiles correspond well with each stress characteristic.

The threshold voltage degradation model of N Channel VDMOSFETs under PBT stress

With the voltage increasing in DC power systems, positive bias temperature instability (PBTI) induced gate oxide degradation of commercial n-channel power vertical double diffused MOSFETs (VDMOSFETs) has been greatly enhanced recently. However, it is not mature in some aspects, e.g., parametric models of PBTI and the turn-around phenomenon are rarely studied. Aiming at these disadvantages, the experimental study and the argument are proposed in this paper. First, the simulation was used to identify and verify the threshold voltage as the characteristic parameter and the accelerated experiment test was conducted to collect data for degradation modeling. Then, a Power law-Arrhenius combined model was adopted in the degradation model to take into account the electrical and thermal influence. Besides that, a two-phase PBTI degradation model was presented, which can describe the turn-around phenomenon. Moreover, the comparison of the estimated remaining useful life (RUL) results with the experimental data verified the accuracy of the developed model.

Hydrogen dissociation and diffusion near the Si/a-SiO2 interface: Understanding degradation in MOSFETs

Hydrogen atom dissociations at the gate/dielectric interface is known to be a degrading process in MOSFET devices. In this work we use molecular dynamics and the ReaxFF forcefield to study hydrogen dissociations as well as diffusion near the gate/dielectric interface. We show that any process that induces hydrogen dissociations (such as radiation) damages the transistors in a fashion very similar to NBTI aging by knocking the hydrogen atoms out of the Si−H bond. We computed the likelihood of dissociation as a function of the initial kinetic energy of hydrogen. We further computed diffusion activation energies, which are in close agreement with previous studies. The analysis of the diffusion paths near the interface reveals mechanisms that are not present in bulk SiO2. In particular, diffusion via oxygen and silicon vacancies with high energy barriers are more prevalent in the vicinity of the interface. This explains the rather high diffusion activation energy of 0.8 ev near the interface compared to the 0.2–0.4 ev in bulk material [1,2].