Channel Length Of MOSFET Research Articles

Measurement of MOSFET constants

A method is described to electrically determine MOSFET channel length, mobility, gate-bias dependence and parasitic series resistance. These four quantities are obtained by curve fitting output resistance measurements over a range of gate biases and channel lengths. Measurements from two gate biases on each of two devices of different channel lengths are sufficient to obtain a full characterization. Thus, the method is well suited for automated testing because of its simplicity and efficiency.

A new method to determine MOSFET channel length

A new method is proposed to electrically determine MOS transistor channel length with both accuracy and convenience. Based on the linear region relationship between effective channel length L eff and channel resistance R chan of an MOS transistor, this method determines L eff by applying relatively large but constant gate voltage to eliminate threshold voltage determination and takes into account external resistance. Comparison of this method with SEM measurement shows very good agreement (within ±0.1 µm resolution limit of our SEM technique).

Threshold-Sensitivity Minimization of Short-Channel MOSFET's by Computer Simulation

This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and extensive use of a two-dimensional device simulation. This structure, which can be realized through DSA technology, obtains adequate tolerances for both the channel length and applied drain voltage in the 1-/spl mu/m channel-length MOSFET; the anticipated channel-length tolerance (Delta L) for maintaining the threshold-voltage fluctuation to within /spl plusmn/10 percent is estimated to be /spl plusmn/0.25 /spl mu/m when V/sub d/ = 5.0 V and gate-oxide thickness t/sub ox/ = 30 nm. With this tolerance, threshold sensitivity to drain voltage drops to one-third in a conventional MOSFET. In a 0.5-/spl mu/m channel-length MOSFET, Delta L is estimated to be /spl plusmn/0.7 /spl mu/m when V/sub d/ = 3.0 V.

Threshold-sensitivity minimization of short-channel MOSFET's by computer simulation

This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and extensive use of a two-dimensional device simulation. This structure, which can be realized through DSA technology, obtains adequate tolerances for both the channel length and applied drain voltage in the 1-µm channel-length MOSFET; the anticipated channel-length tolerance ( \Delta L ) for maintaining the threshold-voltage fluctuation to within ± 10 percent is estimated to be ± 0.25 µm when V_{d} = 5.0 V and gate-oxide thickness t_{ox} = 30 nm. With this tolerance, threshold sensitivity to drain voltage drops to one-third in a conventional MOSFET. In a 0.5-µm channel-length MOSFET, ( \Delta L ) is estimated to be ± 0.7 µm when V_{d}= 3.0 V.

A New Method to Determine Effective MOSFET Channel Length

An accurate and convenient method to determine an effective MOSFET channel length is proposed. This method is based on a computer aided evaluation of an intrinsic MOSFET channel resistance without using special test devices. N-channel silicon-gate MOSFETs were fabricated, and the channel length and its range of device to device scatter were evaluated . To define an effective channel, a simple model of the source-drain (S-D) diffusion layer is proposed. This model shows that the expected transition layer resistance between the S-D diffusion layer and the inverted channel layer agrees with the experimental results. The accuracy of this method is also discussed. It is found to be better than 0.1 µm.

An analysis of the concave MOSFET

The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.

Abstract: Positive photoresist masking properties of high energy, high dose phosphorous-ion implants and their influence on MOS FET device characteristics

The use of a positive photoresist (PR) as a phosphorus-ion implant mask for defining the source and drain of a MOS FET suffers from outgassing and deformation of the resist when high energy ions (150 keV) and a high dose (5×1015 P+/cm2) are involved. This deformation affects the dose uniformity and MOS FET channel length. Here we compare PR masks with those made up of a baked mixture of photoresist and a thermal free radical (PR+TFR) as suggested by Kluge and Elie.1 During the preimplant bake the thermoplastic deformation of the PR+TFR mask is significantly lower than that of the PR mask, but there is no significant difference between the deformation of the two masks during implantation providing the preimplantation bakes are the same. We have made MOS FET’s with channel length as defined by the mask (Lmask) varying from 0.15 to 1.600 mil(3.8 to 4 μm) and have visually measured Lmask following the preimplantation bake. By measuring the MOS FET characteristics (in the linear region) we can determine the effective channel length and compare this with Lmask over a wide range of values. The deformation of the resist can be reduced by using thinner resist and be made negligible by substituting low temperature vacuum baking (prior to implantation) for the conventional high temperature air bake.