MoS2 Transistors Research Articles

Understanding the Impact of Annealing on Interface and Border Traps in the Cr/HfO2/Al2O3/MoS2 System

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance–voltage (C–V) measurements to study electrica...

Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.

Ambipolar MoS2 Field‐Effect Transistor by Spatially Controlled Chemical Doping

Molybdenum disulfide (MoS2) is a widely studied 2D semiconductor, which intrinsically exhibits n‐type transport even using the high work function elemental metals as contacts. It is technically challenging to achieve ambipolar field‐effect transistors with MoS2. Herein, an effective method to prepare p‐doped MoS2 using gold chloride (AuCl3) solution is demonstrated. The doping strength can be controlled well by the process parameters. The AuCl3 doping can also be spatially selected using hexagonal‐boron nitride (h‐BN) capping masks. Subsequently, ambipolar transport can be realized in MoS2 with the coexisting parallel n‐type and p‐type channels. The resulting ambipolar MoS2 transistor presents a high room‐temperature performance, showing a high on/off ratio of 107 and a mobility of 10 s cm2 V−1 s−1 for both electron and hole.

Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors

Two-dimensional semiconductors could be used to fabricate ultimately scaled field-effect transistors and more-than-Moore nanoelectronic devices. However, these targets cannot be reached without appropriate gate insulators that are scalable to the nanometre range. Typically used oxides such as SiO2, Al2O3 and HfO2 are, however, amorphous when scaled, and 2D hexagonal boron nitride exhibits excessive gate leakage currents. Here, we show that epitaxial calcium fluoride (CaF2), which can form a quasi van der Waals interface with 2D semiconductors, can serve as an ultrathin gate insulator for 2D devices. We fabricate scalable bilayer MoS2 field-effect transistors with a crystalline CaF2 insulator of ~2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. Our devices exhibit low leakage currents and competitive device performance characteristics, including subthreshold swings down to 90 mV dec−1, on/off current ratios up to 107 and a small hysteresis. High-performance MoS2 transistors can be created using 2-nm-thick CaF2 as a gate insulator, which forms a quasi van der Waals interface with the 2D semiconductor.

Improved electrical performance of multilayer MoS2 transistor by incorporating Al into host HfO2 as gate dielectric

The effects of incorporating Al into HfO2 as gate dielectric on the back-gated MoS2 transistor are investigated. Hf0.5Al0.5O as gate dielectric exhibits excellent electrical characteristics: on/off ratio of 1.8 × 107, carrier mobility of 49.3 cm2/(V · s), subthreshold swing of 118 mV dec−1, interface-state density of 2.3 × 1012 eV−1 cm−2, due to the Al incorporation into the HfO2 can passivate the defective states induced by oxygen vacancies and improve the dielectric densification and uniformity to obtain an excellent MoS2/Hf1-xAlxO interface. Besides, the intrinsic carrier mobility of 100 cm2 V−1 s−1 and contact resistance of 11.1 kΩ/μm indicates that the contact resistance is a main factor limiting the mobility.

Enhanced Device Stability of Ionic Gating Molybdenum Disulfide Transistors

The application of ion gels as gate dielectrics having an excellent mechanical flexibility and high capacitance to molybdenum disulfide (MoS2) devices has been extensively studied; however, some issues remain unaddressed with regard to device stability such as gate leakage current, hysteresis, and bias stress instability. This study suggests a fabrication process for the ionic gating of the MoS2 device to enhance the device stability by laminating the ion gel film onto the MoS2 transistor using a cut‐and‐stick method and adding a passivation layer to remove unintentional parasitic capacitances generated by the capacitive coupling effect. The ionic gating MoS2 transistor fabricated via this process operates at a low voltage (<1 V) and exhibits superior electrical characteristics such as low gate leakage currents (≈10−11 A), high on–off ratio (>106), and low hysteresis (<0.05 V). To further investigate the device stability, bias stress instability of the ionic gating MoS2 transistor is examined. The charge‐trapping mechanism is the main cause of threshold voltage shifts under gate bias stress.

(Invited) Challenges and Opportunities in the Modeling of Novels Devices and Materials for Logic Applications

In the search for post Si CMOS transistors, different device geometries (FinFETs-on-oxide, nanowires, nanosheets), materials (III-V, Ge, carbon nanotubes), and combination of them have been receiving a lot of attention from the semiconductor industry and from academia. Recently, very promising experimental results have put 2-D single-layer crystals under the spotlight, starting from graphene in 2005 and followed by transition metal dichalcogenides (TMDs), e.g. MoS2 in 2011. Their excellent electrostatic properties, absence of surface dangling bonds, tuneable effective masses and band gaps, and possibility to be stacked on top of each other to form van der Waals heterostructures make 2-D materials particularly appealing for future logic applications, especially at gate lengths below 20 nm. A recent theoretical study based on density functional theory (DFT) [1] predicted that more than 1,800 2-D monolayer compounds might exist, with about 1,000 of them that could be relatively easily exfoliated from their 3-D parents. Among them, some exhibit semiconducting, other metallic or insulating behaviours. Still, it can be expected that hundreds could be suitable as channel material of future ultra-scaled transistors. Exploring the "current vs. voltage" characteristics of all of them to identify the ones that might eventually challenge the current Si FinFET technology is currently not possible at the experimental level: this would require the fabrication of very high number of samples that it would be difficult to compare to each other. Furthermore, the results might strongly depend on the crystal quality, processing techniques, measurement setups, or experimental conditions. All these effects do not allow to properly and unambiguously determine the intrinsic potential of each considered 2-D material. As an alternative, device simulation could be used to support the on-going experimental activity and guide it towards the best material-structure configurations. For that purpose, an accurate, physics-based modelling approach is necessary that does not take fitting parameters as inputs. Ab initio quantum transport solvers lend themselves perfectly to this type of exploratory studies. Such an advanced computer aided design (CAD) tool has been developed to evaluate the figures of merits (ON-current, injection velocity, inversion charge, sub-threshold slope, scalability, energy-delay product...) of future transistors relying on 2-D channel materials [2]. It combines plane-wave DFT calculations, transformations into maximally localised Wannier functions, constructions of device Hamiltonian matrices, and quantum transport simulations. By doing so, a full-band treatment of any single- or multi-layer 2-D compound is possible, without the need for a model parameterisation, as encountered in (semi-)empirical methods such as tight-binding or pseudo-potentials. Here, the properties of conventional TMDs and black phosphorus will be first simulated at the ab initio level and compared to those of strained-Si and III-V FinFETs. Since all theses device configurations will be investigated with the same tool (self-consistent Schrödinger and Poisson solver) and set of approximations, the results do not depend on the simulator features, but only on the intrinsic characteristics of each structure. As next step, the study will be extended by adding the data obtained for 100 other 2-D materials. It will be shown (i) that samples with both high n- and p-type ON-currents can be found, (ii) that they can theoretically outperform Si FinFETs, and (iii) that some of them can be scaled down to gate lengths of 5 nm, while still keeping a decent device behaviour. Finally, since contacting 2-D materials remains an important issue that has not yet been fully resolved, the proposed simulation approach will be employed to highlight the physical mechanisms controlling the transfer of electrons from a metallic layer into a 2-D monolayer. [1] N. Mounet, M. Gilbertini, Ph. Schwaller, D. Campi, A. Merkys, A. Marrazzo, T. Sohier, I. E. Castelli, A. Cepellotti, G. Pizzi, and N. Marzari, "Two-dimensional materials from high-throughput computational exfoliation of experimentally known compounds", Nature Nano. 13, 246 (2018). [2] A. Szabo, Reto Rhyner, and Mathieu Luisier, "Ab initio simulation of single- and few-layer MoS2 transistors: effect of electron-phonon scattering", Phys. Rev. B 92, 035435 (2015).

Relatively Low-Temperature Processing and Its Impact on Device Performance and Reliability

Fabrication of MoS2, ZnO, and IGZO transistors at low enough temperatures that are suitable for large-area/flexible electronics is presented. Evaluating critical processing conditions and approaches on device performance is critical to understanding and improving devices to enable large-area/flexible circuits for the IoT. For MoS2, a study of the implications of photoresist residue on MoS2 in the source/drain contact region was done. Results determined that an O2 plasma exposure in this location can remove the resist residue and create a robust TiOx/MoS2 contact, where an ~15x increase in mobility and ~20x reduction in contact resistance was achieved for O2 plasma treated transistors. Thin-film transistor fabrication of ZnO and IGZO as the semiconductor yielded saturation mobilities of 14.2 and 9.0 cm2/V•s, respectively. Among other parameters, the contact resistance was noticeably lower for ZnO due to its polycrystalline morphology compared to the amorphous IGZO, which was determined to be more resistive.

Selectively Metallized 2D Materials for Simple Logic Devices

We herein demonstrate, for the first time, transparent, flexible, and large-area monolithic MoS2 transistors and logic gates. Each single transistor consists of only two components: a monolithic chemical vapor deposition-grown MoS2 and an ion gel. Additional electrode materials are not required. The uniqueness of the device configuration is attributed to two factors. One is that a MoS2 layer is a semiconductor, but it can be doped degenerately; monolithic MoS2 can thus serve as both the electrodes and the channel of a transistor via selective doping of the material at certain positions. The other is the use of an electrolyte gate dielectric that permits effective gating (<3 V) even from an electrode coplanar with the channel. The resulting monolithic MoS2 transistors yield excellent device performance, including a maximum mobility of 1.5 cm2/V s, an on-off ratio of 105, and a turn-on voltage of -0.69 V. This unique transistor architecture was successfully applied to various semiconductors such as ReS2 and indium-gallium-zinc oxide. Furthermore, the presented devices exhibit excellent mechanical, operational, and environmental stabilities. Fabrication of complex logic circuits (NOT, NAND, and NOR gates) by integration of the monolithic MoS2 transistors is demonstrated. Finally, the monolithic MoS2 transistor was connected to drive red, green, and blue light-emitting diode pixels, which yielded high luminance at a low voltage (<3 V). We believe that the unique architecture of the devices provides a facile way for low-cost, flexible, and high-performance two-dimensional electronics.

Phonon-assisted carrier transport through a lattice-mismatched interface

MoS2 typically exhibits unconventional layer-thickness-dependent electronic properties. It also exhibits layer-dependent band structures including indirect-to-direct band transitions, owing to which the electronic and carrier transport properties of a lattice-mismatched, conducting, two-dimensional junction are distinct with the naturally stepwise junction behaving as a 1D junction. We found distinguishable effects at the interface of vertically stacked MoS2. The results revealed that misorientationally stacked layers exhibited significantly low junction resistance and independent energy bandgaps without bending owing to their effectively decoupled behavior. Further, phonon-assisted carriers dominantly affected the lattice-mismatched interface owing to its low junction resistance, as determined via low-temperature measurement. Our results could facilitate the realization of high-performance MoS2 transistors with small contact resistances caused by lattice mismatching.

Optimization of Electrical Properties of MoS2 Field‐Effect Transistors by Dipole Layer Coulombic Interaction With Trap States

The large negative threshold voltage is one of major electrical factors hindering potential applications of MoS2 transistors in low‐power circuit systems. Here, a strategy by forming an electric dipole layer on the surface of MoS2 is presented to optimize the threshold voltage in monolayer polycrystalline MoS2 field‐effect transistors. The electric dipole in an inert non‐conjugated polymer, perfluoropolyether (PFPE), can interact with trapped electrons in the MoS2 active layer and transfer the traps from shallow into deep states, which remarkably improves the threshold voltage. Otherwise, ab initio calculation and molecular dynamics simulation are employed to investigate the transport properties of MoS2 with PFPE. The calculated results imply that localized electrons are dominantly affected by PFPE, while free electrons are irrelevant. This method with dipole layer provides a pathway to implementation of high‐performance MoS2 transistors for future electronic applications.

Gate-tunable non-volatile photomemory effect in MoS2 transistors

Non-volatile memory devices have been limited to flash architectures that are complex devices. Here, we present a unique photomemory effect in transistors. The photomemory is based on a photodoping effect—a controlled way of manipulating the density of free charges in monolayer using a combination of laser exposure and gate voltage application. The photodoping promotes changes on the conductance of leading to photomemory states with high memory on/off ratio. Such memory states are non-volatile with an expectation of retaining up to 50% of the information for tens of years. Furthermore, we show that the photodoping is gate-tunable, enabling control of the recorded memory states. Finally, we propose a model to explain the photodoping, and we provide experimental evidence supporting such a phenomenon. In summary, our work includes the phototransistors in the non-volatile memory devices and expands the possibilities of memory application beyond conventional memory architectures.

Sub-10 nm Monolayer MoS2 Transistors Using Single-Walled Carbon Nanotubes as an Evaporating Mask.

Transition-metal dichalcogenides are promising challengers to conventional semiconductors owing to their remarkable electrical performance and suppression of short-channel effects (SCEs). In particular, monolayer molybdenum disulfide has exhibited superior suppression of SCEs owing to its atomic thickness, high effective carrier mass, and low dielectric constant. However, difficulties still remain in large-scale stable fabrication of nanometer-scale channels. Herein, a method to fabricate electrodes with sub-10 nm gaps was demonstrated using horizontally aligned single-walled carbon nanotubes as an evaporation mask. The widths of the nanogaps exhibit robust stability to various process parameters according to the statistical results. Based on these nanogaps, ultrashort-channel length monolayer MoS2 field-effect transistors were produced. Monolayer MoS2 devices with a 7.5 nm channel length and a 10 nm thick HfO2 dielectric layer exhibited excellent performances with an ON/OFF ratio up to 107, a mobility of 17.4 cm2/V·s, a subthreshold swing of about 120 mV/dec, and a drain-induced barrier lowering of about 140 mV/V, all of which suggest a superior suppression of SCEs. This work provides a universal and stable method for large-scale fabrication of ultrashort-channel 2D-material transistors.

Flexible Molybdenum Disulfide (MoS2) Atomic Layers for Wearable Electronics and Optoelectronics.

Flexible, stretchable, and bendable materials, including inorganic semiconductors, organic polymers, graphene, and transition metal dichalcogenides (TMDs), are attracting great attention in such areas as wearable electronics, biomedical technologies, foldable displays, and wearable point-of-care biosensors for healthcare. Among a broad range of layered TMDs, atomically thin layered molybdenum disulfide (MoS2) has been of particular interest, due to its exceptional electronic properties, including tunable bandgap and charge carrier mobility. MoS2 atomic layers can be used as a channel or a gate dielectric for fabricating atomically thin field-effect transistors (FETs) for electronic and optoelectronic devices. This review briefly introduces the processing and spectroscopic characterization of large-area MoS2 atomically thin layers. The review summarizes the different strategies in enhancing the charge carrier mobility and switching speed of MoS2 FETs by integrating high-κ dielectrics, encapsulating layers, and other 2D van der Waals layered materials into flexible MoS2 device structures. The photoluminescence (PL) of MoS2 atomic layers has, after chemical treatment, been dramatically improved to near-unity quantum yield. Ultraflexible and wearable active-matrix organic light-emitting diode (AM-OLED) displays and wafer-scale flexible resistive random-access memory (RRAM) arrays have been assembled using flexible MoS2 transistors. The review discusses the overall recent progress made in developing MoS2 based flexible FETs, OLED displays, nonvolatile memory (NVM) devices, piezoelectric nanogenerators (PNGs), and sensors for wearable electronic and optoelectronic devices. Finally, it outlines the perspectives and tremendous opportunities offered by a large family of atomically thin-layered TMDs.

Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

Chemical Vapor Deposition Growth of Large-Area Monolayer MoS2 and Fabrication of Relevant Back-Gated Transistor**Supported by the National Natural Science Foundation of China under Grant No 61774064.

A closed two-temperature-zone chemical vapor deposition (CVD) furnace was used to grow monolayer molybdenum disulfide (MoS2) by optimizing the temperature and thus the evaporation volume of the Mo precursor. The experimental results show that the Mo precursor temperature has a large effect on the size and shape transformation of the monolayer MoS2, and at a lower temperature of <760°C, the size of the triangular MoS2 increases with the elevating temperature, while at a higher temperature of >760°C, the shape starts to change from a triangle to a truncated triangle. A large-area triangular monolayer MoS2 with a side length of 145 μm is achieved at 760°C. Further, the as-grown monolayer MoS2 is used to fabricate back-gated transistors by means of electron beam lithography to evaluate the electrical properties of MoS2 thin films. The MoS2 transistors with monolayer MoS2 grown at 760°C exhibit a high on/off current ratio of 106, a mobility of 1.92 cm2/Vs and a subthreshold swing of 194.6 mV/dec, demonstrating the feasible approach of CVD deposition of monolayer MoS2 and the fabrication of transistors on it.

Ultra-Short Pulsed Laser Annealing Effects on MoS2 Transistors with Asymmetric and Symmetric Contacts

The ultra-short pulsed laser annealing process enhances the performance of MoS2 thin film transistors (TFTs) without thermal damage on plastic substrates. However, there has been insufficient investigation into how much improvement can be brought about by the laser process. In this paper, we observed how the parameters of TFTs, i.e., mobility, subthreshold swing, Ion/Ioff ratio, and Vth, changed as the TFTs’ contacts were (1) not annealed, (2) annealed on one side, or (3) annealed on both sides. The results showed that the linear effective mobility (μeff_lin) increased from 13.14 [cm2/Vs] (not annealed) to 18.84 (one side annealed) to 24.91 (both sides annealed). Also, Ion/Ioff ratio increased from 2.27 × 10 5 (not annealed) to 3.14 × 10 5 (one side annealed) to 4.81 × 10 5 (both sides annealed), with Vth shifting to negative direction. Analyzing the main reason for the improvement through the Y function method (YFM), we found that both the contact resistance (Rc) and the channel interface resistance (Rch) improves after the pulsed laser annealings under different conditions. Moreover, the Rc enhances more dramatically than the Rch does. In conclusion, our picosecond laser annealing improves the performance of TFTs (especially, the Rc) in direct proportion to the number of annealings applied. The results will contribute to the investigation about correlations between the laser annealing process and the performance of devices.

Complementary inverters based on low-dimensional semiconductors prepared by facile and fully scalable methods

Two-dimensional (2D) semiconductors offer great potential in nanoelectronics due to their unique electrical and optical properties mainly attributed to their atomically thin nature. To make use of 2D semiconductors for practical applications, it is highly desired to develop scalable methods for integration of complementary circuits rather than a discrete device. We report a simple, scalable method for fabricating complementary inverters based on n-type monolayer MoS2, grown by a chemical vapor deposition (CVD), and inkjet-printed p-type SWCNTs. The CVD and inkjet printing methods are effectively combined to show the feasibility in terms of the integration of low-dimensional materials for complementary circuits. In the complementary circuits, cost-effectively printed Ag is utilized as the source and drain electrodes for both MoS2 and SWCNT transistors. Both the n- and p-type transistors show decent device characteristics at low operating voltages under ambient conditions. As a result, the complementary inverter composed of MoS2 and SWCNT transistors exhibits excellent performance with a gain over 10, low power dissipation, high noise margins, and switching threshold of 1/2 VDD at a low operating voltage. This successful demonstration of the complementary inverter, the most basic building block in digital circuits, will lead promising 2D semiconductors to practical applications.

Crested two-dimensional transistors.

Two-dimensional transition metal dichalcogenide (TMD) materials, albeit promising candidates for applications in electronics and optoelectronics1-3, are still limited by their low electrical mobility under ambient conditions. Efforts to improve device performance through a variety of routes, such as modification of contact metals4 and gate dielectrics5-9 or encapsulation in hexagonal boron nitride10, have yielded limited success at room temperature. Here, we report a large increase in the performance of TMD field-effect transistors operating under ambient conditions, achieved by engineering the substrate's surface morphology. For MoS2 transistors fabricated on crested substrates, we observed an almost two orders of magnitude increase in carrier mobility compared to standard devices, as well as very high saturation currents. The mechanical strain in TMDs has been predicted to boost carrier mobility11, and has been shown to influence the local bandgap12,13 and quantum emission properties14 of TMDs. With comprehensive investigation of different dielectric environments and morphologies, we demonstrate that the substrate's increased corrugation, with its resulting strain field, is the dominant factor driving performance enhancement. This strategy is universally valid for other semiconducting TMD materials, either p-doped or n-doped, opening them up for applications in heterogeneous integrated electronics.

Effects of Trapped Charges in Gate Dielectric and High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${k}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Encapsulation on Performance of MoS2Transistor

The effects of trapped charges in gate dielectric and high- ${k}$ encapsulation layer on the performance of MoS2 transistor are investigated by using SiO2 with different thicknesses as the gate dielectric and HfO2 as the encapsulation layer of the MoS2 surface. Results indicate that the positive trapped charges in SiO2 can increase the electrons in MoS2 for screening the scattering of charged impurity (CI) in SiO2 and at the SiO2/MoS2 interface to increase the carrier mobility. However, the CI scattering becomes stronger for thicker gate dielectric with more trapped charges and can dominate the electron screening effect to reduce the mobility. On the other hand, with the HfO2 encapsulation, the OFF-currents of the devices greatly increase and their threshold voltages shift negatively due to more electrons induced by more positive charges trapped in HfO2. Moreover, the screening effect of these electrons on the CI scattering results in a mobility increase, which increases with the magnitude of the CI scattering. A 51% improvement in mobility is obtained for the sample suffering from the strongest CI scattering, fully demonstrating the effective screening role of high- ${k}$ dielectric on the CI scattering.