MOS Transistors In Saturation Region Research Articles

MOSFET-only multi-function biquad filter

In this paper, using only seven MOS transistors, second order current-mode LP/BP filter is proposed. The transconductances of the MOS transistors in saturation region are used instead of passive resistors and gate-to-source capacitances are employed instead of passive capacitors. The proposed circuit exhibits important features such as simplicity, reduced chip area and wide frequency range compared to classical analog circuits that require active elements including large number of transistors. Layout of the proposed circuit is drawn using Mentor Graphics IC Station layout editor. AMS 0.35μm process parameters are used during post-layout simulations.

Design of a high frequency low voltage CMOS operational amplifier

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

An analog cell and its applications in analog signal processing

AbstractThis paper presents a straightforward current‐mode CMOS squarer circuit. The proposed circuit exploits the square‐law characteristic of MOS transistor in saturation region. The squarer circuit is then used to implement multiplier and exponential functions. To demonstrate the method, circuits are designed in 0.35 µm CMOS process, using single 3.3 V supply. HSPICE simulations, with level 49 model parameters, confirm the operation of the proposed CMOS circuits. Copyright © 2010 John Wiley & Sons, Ltd.

A CMOS Four Quadrant Current/Transconductance Multiplier

This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental results for 2 μm CMOS technology are provided.