MOS Structures Research Articles

Characterisation of 4H-SiC MOS Capacitor with a Protective Coating for Harsh Environments Applications

Oxygen free Ohmic contacts are essential for the realisation of high performance devices. Ohmic contacts in SiC often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O2 rich ambient at temperatures of 800 °C or less, affecting the electrical and surface characteristics. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOS structures. In order to prevent damage during the high-k formation the use of silicon nitride as a passivation layer, capable of protecting the contacts during annealing, has been investigated. In this work we have investigated and compared silicon nitride protected high-κ dielectric SiC based MOS capacitors with the unprotected SiC MOS devices in terms of electrical and optical characteristics.

Potential changes and chemical bonding features for Si-MOS structure as evaluated from HAXPES analysis

An Au/SiO2/Si MOS structure was fabricated by the thermal oxidation of H-terminated Si(100) surface and the electrode formation, and hard X-ray photo-emission spectroscopy (HAXPES) measurements of MOS structure under the different applied bias conditions were performed systematically to investigate the potential distribution such as the band bending in the MOS structure and the chemical bonding features in the region near the Au/SiO2 interface. And, the measured energy position of HAXPES signals originating from the Au electrode, SiO2, and Si substrate were compared with the calculation results of potential change for ideal MOS structure in consideration of SiO2 thickness and impurity concentration of Si substrate.

Substrate Partitioning Scheme for Compact Charge Modeling of Multigate MOSFETs

A modeling approach for the charge-voltage characteristics of multigate metal-oxide-semiconductor field-effect transistors with complicated cross sections is proposed. Using solutions of linear equations, the substrate region is partitioned into several 1-D MOS structures and the coupling capacitances between these structures are evaluated. It is numerically demonstrated that the set of 1-D MOS structures together with the coupling capacitances yields excellent agreement in the charge-voltage characteristics in all operational regimes. Moreover, further simplification allows us to model the charge-voltage characteristics accurately with only two MOS structures.

Reduction of slow trap density of Al2O3/GeOx/n-Ge MOS interfaces by inserting ultrathin Y2O3 interfacial layers

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (Dit) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new Al2O3/ultrathin Y2O3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) Al2O3/Y2O3/Ge MOS structures with plasma post oxidation (PPO) for introducing Y into GeOx and mitigating slow trapping. Both Dit and slow trap density (ΔNst) in the Al2O3/Y2O3/Ge system are reduced by PPO. A 1.5-nm-thick Al2O3/0.63-nm-thick Y2O3/GeOx/Ge interface can provide a 36% lower amount of ΔNst at Eox of 3×106V/cm with maintaining similar levels of Dit than the control Al2O3/GeOx/Ge interface. It is found that the optimum Y2O3 thickness exists for minimizing ΔNst.

Enhancement of Light-to-Dark Current Ratio Via Coupling Effect for MIS (p) Tunnel Diode Photo Sensors

The current of metal-insulator-semiconductor (MIS) tunnel diode is dependent on the Schottky barrier height and there are different mechanisms which dominate MIS tunnel currents while MIS tunnel diodes were biased at positive and negative voltages. In this work, coupled current-voltage behaviors were observed in a MIS(p) tunnel diode with an MOS structure coupled nearby (1). It was found that MIS(p) saturation tunneling current could be controlled by the voltage bias (VG) of the nearby MOS capacitor. While VG changes, minority carrier distribution at the fringe of the MIS tunnel diode also changes. As a result, by well-controlling VG, the light to dark current ratio Ilight/Idark can be effectively enhanced. In this study, two intensities of illumination on MIS(p) tunnel diodes of three different oxide thicknesses were displayed. It is shown under both intensities of illumination, the light to dark current ratio Ilight/Idark are all effectively enhanced by well-controlling VG. It is also found that the maxima of current ratio Ilight/Idark take place at different values of VG for different intensities of illumination. Coupling effect plays an important role on this phenomenon.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance–voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Failure Mechanism of Nano-Resistor Devices

The failure mechanism of the nano-resistor device formed from the breakdown of the Zr-doped HfO2 high-k dielectric MOS structure has been studied using the accelerated high-voltage stress method. The failure process proceeded from the edge toward the center of the device, which was contributed by the uneven temperature distribution from the difference of the local leakage currents. With the increase of the stress time, the original flat ITO surface showed bumps of which the size increased with the stress time. Eventually, the local region became black because of damages of ITO and related materials. The understanding of the failure mechanism of the nano-resistor device is very important to its reliability and applications.

Normally-Off AlGaN/GaN Mos-Hemts Using ZrO2 Gate Dielectric with Tuneable Charge

GaN-based high electron mobility transistors (HEMTs) are of significant interest for next-generation RF power amplifiers and monolithic microwave integrated circuits (MMICs). The integration of a gate dielectric in a MOS-HEMT device has been shown to offer significantly reduced gate leakage, resulting in improved reliability and reduced off-state power consumption. ZrO2 has attracted increasing attention as a candidate gate insulator for GaN-based HEMTs, due to a high dielectric constant (25), large bandgap (5.9 eV), and high breakdown voltage (15-20 MV/cm). We have previously reported high positive threshold voltage in unpassivated HEMT structures with recessed barrier layers and ZrO2 gate dielectrics deposited using zirconium (IV) tert-butoxide (ZTB) as the Zr precursor [1]. In this work, we compare these devices to structures incorporating the more common tetrakis(dimethylamino)zirconium (TDMA-Zr) precursor, which is expected to exhibit less fixed oxide charge. Combined with the optional barrier recess step, we demonstrate threshold voltage control over a range of 7V for a given HEMT layer structure. We also report the integration of SiNX passivation layers and an evaluation of the dynamic switching performance of the devices. AlGaN/GaN HEMT devices structures were grown on Si substrates by MOCVD, and devices were fabricated following standard GaN device process steps described elsewhere [1]. ZrO2 layers were deposited by atomic layer deposition using both ZTB and TDMA-Zr precursors and deionized water. Ellipsometry and X-ray photoelectron spectroscopy (XPS) were used to verify thickness and identify film stoichiometry. Capacitance-voltage measurements were initially used to characterize the oxide. A dielectric constant of 25 was extracted, and interface trap density was on the order of ~1x1012, dependent upon the nature of the oxide and the surface upon which it was deposited (HEMT structure vs GaN MOS capacitor). Gated Hall measurements were used to characterize the 2DEG mobility and sheet carrier density, both in the HEMT structure and in the recessed region under the gate. The non-recessed devices exhibit comparable current density, transconductance, and ON-resistance. The threshold voltage is shifted positive for device structures incorporating the ZTB-derived ZrO2 film, approaching enhancement mode even without the barrier recess and demonstrating an exceptionally high +4V with a barrier recess. The mechanism for this is proposed to be the presence of negative charge in the oxide film, potentially due to excess oxygen in the film. The presence of such charge was verified on GaN capacitor structures. In contrast, the TDMA-Zr-derived ZrO2 films exhibit a negative VT shift due to the thicker effective barrier, just reaching enhancement mode operation even with a full barrier recess. The breakdown voltage was comparable among all device structures both with and without recess. As expected, the gate leakage was suppressed over 5 orders of magnitude compared to the reference Schottky gated HEMT. Pulsed I-V measurements indicate a degraded current collapse behavior in the ZTB-based devices, which is expected as the negative charge from the oxide would be expected to enhance the charge trapping effect. In contrast, the TDMA-Zr-based device structures exhibit comparable current collapse to the reference device, and possibly even represent an improvement due to reduced trapping under the gate in the MOS structure. Similar behavior in the recessed gate structure indicates minimal permanent damage from the plasma recess etch. In conclusion, we have demonstrated enhancement mode AlGaN/GaN MOS-HEMTs with a thin ALD-ZrO2 gate oxide and barrier recess. The integration of this particular high-k dielectric in the device structure results in a positive threshold voltage shift due to negative charge in the oxide film and at the interface, which when integrated with a barrier recess enables a VT ~+4V while suppressing gate leakage by 4 orders of magnitude compared to a reference Schottky-gated HEMT. 1. T.J. Anderson, et. al. Appl. Phys. Express 9, 071003 (2016)

Resistivity and Barrier Height of Nano-Resistors Made from Zr-Doped HfO2 High-K Dielectric on Si Wafer

Recently, a new type of nano-resistor device made from the high-k dielectric MOS structure was reported [1-5]. Nano-resistors are formed after a dielectric breakdown process. The nano-resistors are conductive paths that allow the current flowing from the substrate to the gate but not in the other direction [4]. In addition to light emission, it shows the antifuse- and diode-like characteristics [3,4]. For the antifuse application, it has a large current ratio of >105 between the “programmed” and “unprogrammed” states [3]. Previously, it was reported that the Schottky contact was formed between the conductive path and the Si substrate after the hard dielectric breakdown [6]. In this paper, authors investigated the resistivity of the nano-resistor surrounded by the Zr-doped HfO2 (ZrHfO) high-k dielectric and its Schottky contact barrier height with Si. The nano-resistors were formed from the dielectric breakdown of a MOS capacitor with the ZrHfO high-k film deposited on top of a p-type <100> Si (11-20 Ω∙cm) wafer. The detailed fabrication process of the 300 µm-diameter MOS capacitor and the nano-resistor formation step could be found in refs. 1-5. The sample surface was imaged with the JEOL JSM-7500F SEM after being stressed at the gate voltage (Vg ) of -20 V for 20 min. The I-V curve was measured with an Agilent 4155C semiconductor parameter analyzer. Figure 1 shows the top view of the device after being stressed at Vg = -20 V. Many tiny bumps are evenly distributed across the electrode surface. Each bump correspond to a nano-resistor of which the rough surface is formed from the high local temperature generated from the current flow [1]. The actual nano-resistor is located in the center of the bump and is much smaller than the size of the bump [5]. The total cross-sectional area ratio of bumps to the gate in the Fig. 1 structure is estimated to be approximately 0.04443. Figure 2 shows the I-V curve of the nano-resistor device. In the large voltage range, the current increases linearly with the increase of the magnitude of Vg (|Vg |). It has a constant resistance (Rs ) of 396.6 Ω. It is composed of several resistors connected in series: the bulk Si wafer, the Schottky contact between the Si and the nano-resistor, the nano-resistor, the ohmic contact between the nano-resistor and the gate, and the ITO gate electrode. The bulk Si resistance can be calculated based on ref. 7. At the large |Vg |, the Schottky contact resistance is negligibly small compared with other resistances. If the ohmic contact and gate electrode resistances are also neglected, the total resistance of the nano-resistors can be estimated. We assume that each nano-resistor has the same resistivity. Then, the resistivity of the nano-resistor is estimated to be 2673–7075 Ω∙cm, which is in the order of 103 Ω∙cm. At the low |Vg | range, we used the Schottky contact equation to fit the device’s I-V curve, as shown in equations 1 and 2 [7]. The voltage drop across the Schottky contact is taken as V-IRs . Figure 3 shows that the Schottky contact equation fits well with the experimental data and the nano-resistor has a barrier height of 0.66 eV on Si. In summary, the resistivity and barrier height of the nano-resistor can be estimated from the experimental data based on some basic assumption of the material properties. [1] Y. Kuo et al, APL, 102, 031117 (2013). [2] Y. Kuo, IEEE TED, 62, 3536-3540 (2015). [3] Y. Kuo, ECST, 67, 183 (2015). [4] Y. Kuo, ECST, 69, 23 (2015). [5] C.-C. Lin et al, APL, 106, 121107 (2015). [6] A. Avellán et al, IEEE EDL, 29, 366 (2008). [7] S. M. Sze et al, Physics of Semiconductor Devices, John Wiley & Sons, New Jersey (2007). Figure 1

Interface properties of NO-annealed 4H-SiC (0001), (112¯), and (11¯00) MOS structures with heavily doped p-bodies

We investigated electrical characteristics of nitric oxide (NO)-annealed silicon carbide (SiC) (0001), (112¯0), and (11¯00) metal-oxide-semiconductor field effect transistors (MOSFETs) with heavily doped p-bodies (NA = 1 × 1017–3 × 1018 cm−3). Regardless of crystal faces or off-direction, the channel mobility decreased for higher acceptor density. We evaluated the interface state density (Dit) very near the bottom edge of 2-dimensional density of states (2D-DOS) in the conduction band of SiC from the low-temperature subthreshold slope of the MOSFETs. When the acceptor density of the p-body of the MOSFET is increased, the energy levels of 2D-DOS increase due to a stronger quantum confinement effect. Accordingly, the carriers in the heavily doped channel are influenced by the interface states located at higher energy levels. In the SiC MOS structures, the Dit values significantly increase near the conduction band edge (EC). Thus, MOSFETs on heavily doped p-bodies are affected by the higher density of Dit, leading to substantially lower mobility.

The Influence of the multilayer ZnO-HfOx structure on the characteristics of a light-emitting device

A MOS structure device with a ZnO-HfOx layer was fabricated on a p-type silicon substrate. Current (i.e., conductive) paths formed after the breakdown of the dielectric layer under a voltage and thermal-induced emission of broadband light, including visible and near-IR wavelengths. To investigate the influence of the ZnO-HfOx layer on a device’s light-emitting characteristics, we prepared devices with one, two and three layers of ZnO-HfOx thin film on a p-type silicon substrate. We then measured the light emission, the emission spectrum, the I–V curves and the microstructure. The results show that the range and peak wavelength of the emission spectra from devices with different numbers of ZnO-HfOx layers are the same. Under the condition of a fixed total thickness of HfOx, luminous intensity increases with increasing number of ZnO-HfOx layers. Multilayer ZnO-HfOx can cause the ZnO grains to diffuse more into the HfOx layer, which is beneficial for the formation of current paths and increases the luminous intensity.

Reduction of interface state density in SiC (0001) MOS structures by post-oxidation Ar annealing at high temperature

We found that post-oxidation Ar annealing at high temperature is effective in reducing the interface state density (Dit) near the conduction band edge (EC) of SiC (0001) MOS structures. The Dit reduction effect is comparable to that of nitridation process (annealing in nitric oxide (NO)) which has been a standard in SiC MOS technologies, without introducing any foreign atoms into the interface/oxide. The generation of fast interface states, which have been pointed out as a problem of nitridation process, is suppressed in the case of Ar annealing. In the proposed method, the final Dit values are mainly determined by the Ar annealing temperature rather than the initial oxidation temperature. The Dit values are not sensitive to the cooling speed, which means that rapid cooling is not necessary in the proposed method.

Ultimate Pixel Based on a Single Transistor With Deep Trapping Gate

Simulation results are reported on the trapping MOS structure, which is a new metal insulator semiconductor pixel concept. Using a quantum well (QW) as a buried gate, I will show that this device is the ultimate design for photon sensitive pixels when pixel size is the criterion. The device reduces to only one transistor, which acts as a charge collecting device and amplifier and it is randomly addressable. I study here the device based on a silicon–germanium material couple, but the principle can be implemented with other materials. The photo-generated charge is collected by a buried gate based on a QW, and is able to selectively localize carriers that modulate the source–drain current in the readout mode. The device simulation is based on the quantum density gradient method, which had shown to give good results with respect to previous experimental studies. They are applied in the case of thin (20 nm) buried SiGe layers, which is comparable with an earlier structure using traps for charge retention. The simulation of this structure based on actual silicon germanium technologies is robust enough to assess the practical feasibility of the device. Downscaling to deep submicrometer sizes is possible with favorable consequences regarding the pixel’s sensitivity.

Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs

The subthreshold performance of graded-channel dual-material double-gate (GCDMDG) MOSFETs is examined through two-dimensional (2D) analytical modeling of subthreshold-current (SC) and subthreshold-swing (SS). The potential function obtained by using the parabolic approach to solve the 2D Poisson's equation, has been used to formulate SC and SS characteristics of the device. The variations of SS against different device parameters have been obtained with the help of effective conduction path parameter. The SC and SS characteristics of the GCDMDG MOS transistor have been compared with those of the dual-material double-gate (DMDG) and simple graded-channel double-gate (GCDG) MOS structures to show its better subthreshold characteristics over the latter two devices. The results of the developed model are well-agreed with the commercially available SILVACO ATLAS™ simulator data.

Investigation of the Surface Defects in N-Channel MOS Transistors Under Long-Term Low-Dose-Rate Irradiation

Gamma-radiation is commonly used to study surface defects in MOS transistors. Early experiments show two stages of surface-defect formation in a MOS structure under low-intensity gamma irradiation (Popov &amp; Vin, 2014; Popov, 2016). On the first stage the defect formation take place on interface Si-SiO2 from the oxide side. This process is described by an exponential dependence (Rashkeev et al., 2002). In the second stage “additional” surface defects are formed from the Si side. Radiation defects of silicon migrated to interface Si-SiO2 from the semiconductor.The goal of this paper is investigation of surface-defect formation in a MOS transistor using the changing of surface electron mobility.

High Photoresponsivity Ge-dot PhotoMOSFETs for Low-power Monolithically-Integrated Si Optical Interconnects

We report the demonstration of high-photoresponsivity Ge-dot photoMOSFETs in a standard MOS configuration for the detection of 850–1550 nm illumination. Each device has a self-organized, gate-stacking heterostructure of SiO2/Ge-dot/SiO2/SiGe-channel which is simultaneously fabricated in a single oxidation step. Superior control of the geometrical size and chemical composition for our Ge nanodots/SiO2/Si1-xGex-shell MOS structure enables the practically-achievable, gate-stacking design for our Ge-dot photoMOSFETs. Both the gate oxide thickness and the diameter of the Ge dots are controllable. Large photocurrent enhancement was achieved for our Ge-dot photoMOSFETs when electrically-biased at ON- and OFF-states based on the Ge dot mediating photovoltaic and photoconductive effects, respectively. Both photoelectric conversion efficiency and response speed are significantly improved by reducing the gate-oxide thickness from 38.5 nm to 3.5 nm, and by decreasing Ge-dot size from 90 nm to 50 nm for a given areal density of Ge dots. Photoresponsivity () values as high as 1.2 × 104 A/W and 300 A/W are measured for 10 nW illumination at 850 nm and 1550 nm, respectively. A response time of 0.48 ns and a 3 dB-frequency of 2 GHz were achieved for 50 nm-Ge-dot photoMOSFETs with channel lengths of 3 μm under pulsed 850 nm illumination.

Thin SiO2/a-Si:H/SiO2 multilayer insulators obtained by electron cyclotron resonance chemical vapor deposition at room temperature for possible application in non-volatile memories

In this work we present electrical and morphological characterization of thin multilayer structures, SiO2/a-Si:H/SiO2, with possible applications in non-volatile memories devices. All films were obtained by Electron Cyclotron Resonance Chemical Vapor Deposition technique at room temperature. To induce structural changes in the amorphous silicon layer, the gate stacks were subjected to high temperature furnace annealing at 800°C and 1100°C.Three-layer MOS structures were patterned by lithography and subjected to a sintering process in forming gas for 20min. The structures annealed at high temperature present a memory window in their capacitance-voltage dependencies, which means that these structures could have a possible application as gate insulators in non-volatile memory devices. The morphology of the amorphous layers was studied by atomic force microscopy and scanning electron microscopy which revealed increase of the surface roughness and modifications in the a-Si:H layer after the high temperature process.

Schottky bipolar I-MOS: An I-MOS with Schottky electrodes and an open-base BJT configuration for reduced operating voltage

In this paper, we have proposed a novel impact ionization MOS (I-MOS) structure, called the Schottky bipolar I-MOS, with Schottky source and drain electrodes and utilizing the open-base bipolar junction transistor (BJT) configuration for achieving reduction in the operating voltage of the I-MOS transistor. We report, using 2-D simulations, a low operating voltage (∼1.1 V) and a low subthreshold swing (∼3.6 mV/Decade). For the corresponding p-i-n I-MOS, the operating voltage is ∼5.5 V. The operating voltage of the Schottky bipolar I-MOS is the lowest reported operating voltage for silicon based I-MOS transistors. The nearly 80% reduction in the operating voltage of the Schottky bipolar I-MOS makes it suitable for applications requiring low operating voltages. The Schottky bipolar I-MOS is also expected to have an improved reliability over the p-i-n I-MOS since high energy carriers, induced by impact ionization near the drain, do not have to pass under the gate region in the channel. The use of Schottky contacts instead of heavily doped source and drain regions and the low channel doping level reduces the required thermal budget for device fabrication. The low operating voltage, low subthreshold swing and possibly improved reliability of the Schottky bipolar I-MOS, makes it a potential solution for applications where steep subthreshold slope transistors are being explored as alternative to the conventional MOS transistor.

Erratum to: Study of various technological parameters on the C-Vg and the G-Vg characteristics of MOS structures

Erratum to: Study of various technological parameters on the C-Vg and the G-Vg characteristics of MOS structures

Oxide trap states versus gas sensing in SiC-MOS capacitors – The effect of N- and P- based post oxidation processes

A novel hydrogen sensor based on Pd/SiO2/SiC capacitors with field oxide ramp termination was fabricated, and a systematic investigation of the most utilized post oxidation annealing (POA) processes, in N or P based ambient, was realized in order to propose the most appropriate technological approach. The experimental structures were electrically characterized, on the one hand to examine the gate oxide quality and, on the other hand, to test the device response as hydrogen sensor. We demonstrated that, whereas the POCl3 based POA leads to significant improvement of the SiO2/SiC interface, and moreover of the oxide breakdown electric field, the 1100°C N2 based POA assures the highest response as hydrogen sensor, both at room temperature and 200°C. Both interface states density and oxide charges present in the MOS structures have been determined and their influence on the observed phenomena have been discussed.