MOS Gate Research Articles

(Invited) Gate Stack Technology for Advanced GaN-Based Mos Devices

GaN-based power devices have received much attention for their application in the next-generation high-frequency and high-power devices. Recently, AlGaN/GaN heterojunction field-effect transistors (HFETs) with Schottky gate structures have been implemented into modern wireless communication systems. However, their applications are restricted because of large gate leakage current through the Schottky contacts and their normally-on operation. To overcome these limitations, MOS gate stacks on GaN-based materials have been intensively studied. Moreover, normally-off vertical power MOSFETs on free-standing GaN substrates have become a hot topic in power electronics. In contrast with the Si-based semiconductors, deposition of wide bandgap insulators on the AlGaN and GaN surfaces is thought to be a plausible method for fabricating MOS gate stacks. Among the various insulating materials, Al2O3 and SiO2 exhibit a sufficiently wide bandgap and thermal stability for MOS device applications. However, it is well known that Al2O3 involves an essential problem of electron trapping, thus leading to significant Id-Vg hysteresis and Vth instability. In addition, poor electrical properties of GaN-based MOS devices have been reported even for the well-established ALD-Al2O3 and CVD-SiO2 films. We have investigated suitable insulating materials and deposition methods for AlGaN/GaN MOS-HFETs and GaN-MOSFETs. This paper reviews our recent findings on gate stack engineering for advanced GaN-based MOS devices and discusses a common guiding principle to improve device performance and reliability. We implemented nitrogen incorporated Al2O3 (AlON) gate dielectrics into the AlGaN/GaN MOS-HFETs and successfully improved the performance and reliability of the devices. Our physical and electrical characterizations revealed superior thermal stability of the AlON/AlGaN interface and the importance of conducting dielectric deposition under a reactive nitric atmosphere to suppress intermixing at the interface. Recently, we demonstrated high current and high voltage (20A/730V) normally-off AlGaN/GaN MOS-HFETs with the AlON gate dielectrics. For fabricating GaN-MOS structures, oxidation of the GaN surface is a fundamental method of obtaining gate insulators, but severe drawbacks, such as insufficient conduction band offset at GaOx/GaN interfaces and rough surface morphology have been pointed out. Thus, we proposed GaN-MOS structures with thin GaOx interlayers, in which oxide interlayers were formed by oxidation of GaN surface prior to SiO2 deposition. We also found that high-quality SiO2/GaOx/GaN stacked structures were formed by optimizing conditions for plasma-enhanced CVD of SiO2 films. Consequently, well-behaved C-V curves with negligible hysteresis and frequency dispersion were obtained. Moreover, an extremely low interface state density (< 1010 cm-2eV-1) and an improved reliability in terms of reproducibility and robustness against dielectric breakdown were achieved by rapid thermal annealing of SiO2/GaOx/GaN MOS devices.

High Density Formation and Magnetoelectronic Transport Properties of Fe3Si Nanodots

The application of group-IV based metallic-nanodots (NDs) such as silicide- and germanide-NDs to a floating gate in MOS memories has been attracting much attention as charge retention characteristics can be improved and they can be compatible with Si-based semiconductor devices [1]. By replacing nonmagnetic NDs with ferromagnetic NDs, floating gate MOS memories can have the new functionality to control charging and discharging properties in NDs floating gate and to improve retention characteristics by the tunnel magnetoresistance effect between NDs and ferromagnetic gate electorodes [2]. Recently, Fe3Si-NDs have received much attention as the promising materials for application to the Si-based spintronics and/or magnetic memory devices such as magnetoresistive random access memory [3]. Previously, we demonstrated the self-assembling formation of metal (Ni, Pt, Pd, Co and Fe) NDs on thermally grown SiO2 with an areal density as high as ~1012 cm-2 by simply exposing ultrathin metal films to remote H2 plasma (H2-RP) without external heating [4]. In this work, we extended our research to form high density Fe3Si-NDs and to study their magnetization and local I-V characteristics measured with a magnetic probe under external magnetic field application. After conventional wet-chemical cleaning steps for p-type Si(100) wafers, a ~3.6nm-thick SiO2 layer was grown at 850 ˚C. After that, a ~2.0nm-thick Fe layer was first deposited uniformly on the SiO2 layer by electron beam evaporation, and then uniformly with a ~2.0nm-thick amorphous Si (a-Si) layer was covered without air exposure. Subsequently, a ~1.5nm-thick Fe layer was deposited, where the film thicknesses were designed with stoichiometric ratio of Fe:Si=3:1. The Fe/a-Si/Fe trilayer stack was exposed to a H2-RP without external heating. By exposing the trilayer stack to the H2-RP, the formation of NDs with an areal density as high as ~5×1011 cm-2 and with an average height of ~10 nm was observed. Considering the fact that the temperature was raised up to ~480 ˚C in the case of a Fe foil during H2-RP exposure, this result suggests that Fe-Si alloying was promoted with agglomeration by cohesive action of Fe and Si atoms on the SiO2 surface during the H2-RP exposure. In addition, by X-ray diffraction and magnetization measurements, the formation of DO3-orderd NDs was confirmed. To evaluate the local electron transport properties of the DO3-orderd Fe3Si-NDs, a CoPtCr-coated Si cantilever was contacted with the sample surface and kept at the same position, and the I-V characteristics were measured at room temperature, where electrons are injected from the tip. Without any external magnetic field application, the current level was slightly increased with tip bias over ~-3.5 V. When applying a magnetic field of 0.5 kOe in the same direction as the tip magnetization, a distinct increase in the current level was detected, namely, the threshold voltage which is defined as a bias voltage at 0.1 nA was decreased from -4.0 to -0.3 V. With an increase in the magnetic field over 0.6 kOe, no further changes in the I-V curve were observable, which means that the resistance was kept at a significantly decreased level under magnetic fields of 0.5k Oe and over. When the CoPtCr-coated tip was replaced by a Rh-coated tip, almost no change was detected in the I-V curve by the application of a magnetic field of 4.5 kOe, irrespective of the field direction. We also confirmed a remarkable decrease in the current level and an almost complete recovery to the initial current level by applying a magnetic field of 0.5 kOe in the opposite direction to the first magnetization at 0.5kOe. Noted that, when the magnetic field of 0.5 kOe was applied in the same direction again, remarkable increase in the current level was observed. Here, the magnetization direction of the CoPtCr-coated tip is not affected by the magnetic field of 0.5 kOe. Therefore, the observed increase and decrease in the current level, namely, the change in the magnetoresistance can be interpreted in terms that the magnetization of the Fe3Si-NDs was aligned in parallel or antiparallel to that of the CoPtCr-coated tip by the external magnetic field.

On/Off Current Ratio Enhancement By Reducing Electrode Separation in Gate-Controlled MIS Tunnel Transistor

Saturation current of a MIS (p) tunnel diode is strongly dependent on the Schottky barrier height. It was found a gate MOS capacitor near an MIS tunnel diode may affect the saturation current of the tunnel diode. It was supposed that the increase of electron diffusion from a gate MOS capacitor will cause the decrease of the Schottky barrier height and lead to the increase of saturation current [1]. Furthermore, transistor characteristic of this structure was also proposed [2]. By varying gate bias, electron diffusion current varies as well. Since two current states of the tunnel diode occurs, this device can be considered as a transistor. In this work, different gap distances between gate and MIS tunnel diode were studied. It was found that a smaller gap distance may lead to a stronger couple effect. Hence, reduction of gap distance can both enhance tunnel diode saturation current and the Ion / Ioff ratio of the gate-controlled MIS tunnel transistor. The schematic top view and cross section of the gate-controlled MIS tunnel transistor is shown in Fig. 1. We named the inner MIS tunnel diode drain and the outer ring gate. The radius of the inner circle, R1, is 85μm. The gap distance, S, is varying from 5μm to 25μm. The radius of the outer ring, R2, is (585+S)μm. Fig. 2(a) shows ID versus VD with gate floating. The sample without gate structure is denoted as no ring. It can be regard as the gap distance is infinity. Fig. 2(b) shows the saturation current ID,sat versus gap distance of two different oxide thickness. We found that the saturation current increases as the gap distance reduces. Fig. 2(c) and (d) shows the schematic of the mechanism, which can be explained by couple effect. When the gap distance reduces, couple effect becomes stronger, and the electron diffusion from gate’s inversion layer to drain increases, which leads to a larger drain saturation current. Fig. 3(a) shows the ID-VG of the gate-controlled MIS tunnel transistor for different gap distances and VDS’s. It was shown that there are on state and off state for ID. For the on state, the gate bias voltage is around 0V, and the gate MOS capacitor is in inversion region, which introduces a large number of electron to couple to drain. We found that when VDS is smaller than Vsat, ID are irregular because ID do not saturate so it do not follow the rule as observed in Fig. 2(b). However, when VDS is larger than Vsat, drain current becomes ID,sat and increases with the reduction of gap distance. For the off state, gate bias is near VFB, the gate MOS capacitor is close to accumulation region. In this situation, the electron concentration underneath gate is less than the electron concentration in bulk np0. Only a little electron diffusion from the gap region to drain, and leads to a quite low ID. The off current is therefore decreases as the gap distance reduces. Fig. 3(b) shows the schematic of the mechanism. When the gap distance becomes smaller, the electron concentration of the gap region decreases due to the stronger couple impact of the gate MOS capacitor, and leads to the decrement of ID. We called this phenomenon as strong couple effect. Fig. 3(c) and (d) show Ion and Ioff versus gap distance and the Ion / Ioff ratio of drain current of different oxide thickness. It is found that for the smaller gap distance, we got smaller Ioff and larger Ion, and therefore a larger Ion / Ioff ratio of the gate-controlled MIS tunnel transistor. Moreover, in Fig.3(c), it was found that when oxide thickness increases, Ion increases and Ioff decreases, so a larger Ion / Ioff ratio can be obtained. For a gate-controlled MIS tunnel transistor, we use the bias of gate to control the drain MIS tunnel diode by couple effect. In this work, we found that reduction of gap distance can enhance the couple effect of on state and enhance strong couple effect to reduce the off state current. A large Ion / Ioff can be expected. In conclusion, the design of proper small gap distance is the way to improve the performance of a gate-controlled MIS tunnel transistor. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. Most 105-2221-E-002-180-MY3 and 106-2221-E-002-196-MY3. [1] C. S. Liao and J. G. Hwu, ECS Trans., 75(5), 77 (2016) [2] C. S. Liao and J. G. Hwu, IEEE Trans. Electron Devices, 62, 2061 (2015) Figure 1

Square root circuit using FGMOS translinear principle

A novel square root circuit using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. FGMOS transistors are being utilized in a number of new and exciting analog applications. These devices are available in standard CMOS technology because they are being widely used in digital circuits. FGMOS structures are also known as multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. Thus floating gate devices are now finding wider applications by analog researchers. The FGMOS drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only four FGMOS transistors in proposed square-root circuit. The main feature of this remarkably simple square root circuit is to reduce the errors generated by the second order effects in the current mode circuits employing translinear loop.

Performance Improvement and Sub-60 mV/Decade Swing in AlGaN/GaN FinFETs by Simultaneous Activation of 2DEG and Sidewall MOS Channels

This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 1010, and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 $\text{m}\Omega \cdot \text {cm}^{2}$ .

JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.

Simulation Study of a Power MOSFET with Built-in Channel Diode for Enhanced Reverse Recovery Performance

A new silicon power MOSFET architecture is proposed by introducing a built-in channel diode through a dummy MOS gate electrically coupled to the source. The oxide thickness of the channel diode is reduced to obtain a desired turn-ON voltage and attenuate the minority carrier injection from the PN junction body diode. Consequently, the proposed MOSFET is able to deliver superior reverse recovery characteristics, including reductions in reverse recovery charge ( $Q_{\sf RR}$ ) and peak reverse recovery current ( $I_{\mathrm{ RRM}}$ ) by a factor of ~4.2 and ~2.6, respectively. The breakdown voltage (232 V) of the proposed MOSFET is the same as the conventional MOSFET. The on-resistance of the proposed MOSFET (8.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$ ) is only slightly increased compared with conventional MOSFET (8.0 $\text{m}\Omega \cdot \text {cm}^{{2}}$ ). The gate-to-drain charge ( $Q_{\sf GD}$ ) and gate charge ( ${Q} _{\mathsf {G}}$ ) are reduced by a factor of ~7.2 and ~3.9, respectively. Significantly improved figures of merit ( ${R} _{ON} \times {Q}_{\mathsf {G}}$ and ${R} _{ON} \times {Q}_{\mathsf {GD}}$ reduced by a factor of ~3.7 and ~6.8, respectively) are obtained in the proposed MOSFET. The device concept and characteristics are systematically analyzed with numerical TCAD simulations.

Inertial sensing MEMS device using a floating-gate MOS transistor as transducer by means of modifying the capacitance associated to the floating gate

In this work, a novel application of floating gate MOS transistors is presented. An inertial sensor with an embedded FGMOS was designed, simulated and fabricated using commercially available CMOS technology, like the ON Semiconductor 0.5 µm, two poly, three metal, N-well, post-processed using a surface micromachining etchant to obtain a CMOS-MEMS chip, and tested. COMSOL multiphysics was used for electro-mechanical evaluation of the inertial system, PSPICE for electrical behavior analysis, Keithley instruments for electrical characterization, and Labview for data acquisition for electrical characterization. In this work, it is demonstrated that an embedded FGMOS can be used to correlate drain current either for static or dynamic inertial parameters. The presented work demonstrates the feasibility to change the coupling coefficient of the FGMOS by means of a MEMS structure, like an accelerometer, to convert displacement into an electrical signal, being suitable for integration in more complex systems.

Analysis and measurement of a photo diode used as a control gate in a floating–gate MOS transistor

This paper reports a new operating use regarding the floating–gate MOS transistor (FGMOS). Here it is demonstrated that the typical open circuit voltage (VOC) of a CMOS integrated photo sensor can be coupled to the floating gate of a FGMOS. Several photo sensors structure designs are studied and measured. Results demonstrated that the threshold voltage of the transistor can be modulated optically with a series array of photo sensors to increase the coupled voltage. Therefore, a micro solar cell integrated with a CMOS technology can be used as a control gate giving an optical alternative to modulate the I–V characteristics of a FGMOS, extending the reliability of this device beyond the known injection phenomena commonly used to program it. Also, more than one control gate can be used with only one transistor, giving opportunity to explore the convenience to use this proposal within a pixel design since only one transistor is used, with its floating gate as a summing node.

(Invited) Impact of the Metal Gate on the Oxide Stack Quality Assessed by Low-Frequency Noise

It is well-established that the gate oxide quality and reliability strongly depend on the type of high-k and interfacial oxide layer, the deposition method and the implementation of possible post-deposition heat or passivation treatments. As a result, the low-frequency noise magnitude may be largely affected by the gate stack processing details [1]. What is less studied is the impact of the gate material itself on the gate stack quality. Early assessments already indicated an impact of the number of TiN Atomic Layer Deposition (ALD) cycles on the noise Power Spectral Density (PSD) [2]. It is the aim of the present work to review the low-frequency noise of High-k/Metal Gate (HKMG) MOS transistors with emphasis on the role of the specific gate metal. Devices with different architectures (planar, FinFET and NanoWire (NW) FETs) will be considered in addition to the gate first versus gate last integration [3.4] As a first example, the impact of the W plug processing on the LF noise for planar pMOSFETs is shown in Fig. 1. The current noise PSD (SI) in linear operation (VDS=-0.05 V) at a frequency f=10 Hz is shown to become higher for the B2H6 precursor case, compared with the W deposition with SiH4 precursor. The higher noise is interpreted in terms of a higher oxide trap density, which is evidenced by the hump at about 100 mA drain current (ID), which is thought associated with a gate oxide trap, causing a Random Telegraph Signal (RTS). The impact on the gate stack quality (noise) of high-k Silicon-on-Insulator (SOI) and bulk FinFETs is shown in Figs 2 [5] and 3,4 [6], respectively. In the first case, the effective oxide trap density, derived from the input-referred voltage noise PSD increases with the TiN thickness, which also results in a degradation of the static characteristics, i.e., the low-field electron mobility [5]. Even for input-output (IO) devices with a rather thick thermal oxide, the gate material can play a strong role in the noise: comparing Figs 3 and 4, it is clear that both the magnitude and the slope (frequency index) of the spectra are different for a pFinFET with a standard TiN gate versus a TaN one. It will be shown that the latter devices may yield a better gate stack quality (a lower trap density) which becomes similar to that of a SiO2/polysilicon reference. Ultimately, the NW architecture will take over at the end of the Roadmap due to superior gate control of the short-channel effects. Again, it has been shown that for NWFETs the gate metal may have a strong effect on the oxide trap density, as derived from 1/f noise [7,8]. An example is given in Fig. 5, showing a clear correlation between the DC parameters (low-field mobility) and the oxide trap density (Not) derived from the 1/f noise PSD. A more detailed study of the trap density profile in Fig. 6 reveals an increase of Not towards the metal gate for the TiN device, which is absent for the TiAl case. This suggests a possible oxygen scavenging effect of Ti on the gate stack [9], creating an excess of “noisy” oxygen vacancy centers in the high-k layer.

Comprehensive Capacitance–Voltage Simulation and Extraction Tool Including Quantum Effects for High- $k$ on SixGe1−x and InxGa1−xAs: Part II—Fits and Extraction From Experimental Data

Capacitance-voltage ( $C$ – $V$ ) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of interface traps ( ${D}_{ \rm {it}}$ ), and effective gate work function can all be extracted from experimental $C$ – $V$ curves. However, to extract these gate-stack parameters accurately, the correct models must be utilized. In Part I, we described the modeling and implementation of a $C$ – $V$ code that can be used for alternative channel semiconductors in conjunction with high- $k$ gate dielectrics and metal gates. Importantly, this new code (CV ACE) includes the effects of nonparabolic bands and quantum capacitance, enabling accurate models to be applied to experimental $C$ – $V$ curves. In this paper, we demonstrate the capabilities of this new code to extract accurate parameters, including EOT and ${D}_{ \rm {it}}$ profiles from experimental high- $k$ on Ge and In0.53Ga0.47As gate stacks.

(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable. In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected. For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12]. We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds. For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices. This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.

Evaluation of Schottky barrier height on 4H-SiC m-face for Schottky barrier diode wall integrated trench MOSFET

We proposed an Schottky barrier diode wall integrated trench MOSFET (SWITCH-MOS) for the purposes of shrinking the cell pitch and suppressing the forward degradation of the body diode. A trench Schottky barrier diode (SBD) was integrated into a trench gate MOSFET with a wide shielding p+ region that protected the trench bottoms of both the SBD and the MOS gate from high electrical fields in the off state. The SBD was placed on the trench sidewall of the plane (m-face). Static and transient simulations revealed that SWITCH-MOS sufficiently suppressed the bipolar current that induced forward degradation, and we determined that the optimum Schottky barrier height (SBH) was from 0.8 to 2.0 eV. The SBH depends on the crystal planes in 4H-SiC, but the SBH of the m-face was unclear. We fabricated a planar m-face SBD for the first time, and we obtained SBHs from 1.4 to 1.8 eV experimentally with titanium or nickel as a Schottky metal.

A New Quality Metric for III–V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET

This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion ( $\text{D}_{\mathrm {eff}}$ ) evaluated in the accumulation region of capacitance–voltage (C–V) measurements of III–V MOS devices. ${D} _{\mathrm {eff}}$ is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al2O3, and the recently reported ASM-imec interfacial layer (IL) with HfO2 are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al2O3 or a bi-layer stack of Al2O3/HfO2 on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks.

A study of the electrical properties of self-biased channel MOS diodes for solar-cell applications

AbstractWe propose two types of low-cost, low-loss diodes as alternatives to Schottky barrier diodes (SBDs) for use as bypass diodes connected in parallel with solar-cell panels. Both of our proposed devices are self-biasing channel MOS diodes consisting of an n-channel MOS structure that features three-terminal operation combined with a DMOS cell structure exploiting self-biasing effects. By reducing the threshold voltage of the MOS gate, these devices feature lower on-voltages and lower rates of growth in the reverse leakage current with increasing temperature, thus preventing thermal runaway. To investigate the properties of our devices, we used a device simulator to analyze their performance as bypass diodes for a solar-cell panel. Our results indicate that when a shadow partially covers the cell, the current flowing on the load side of the solar-cell panel is about 50% larger than that observed for a Cr SBD, indicating the potential for significantly improved performance.

シリコンIGBTの最新技術

IGBT as the representative of the MOS-bipolar device has widely used for power conversion system, because it has the high controllability as MOS gate device and high breakdown voltage with low ON resistance as bipolar device simultaneously. IGBT has the potential to satisfy so many requirement such as low loss, low switching noise, high breakdown voltage, low cost, high efficiency and high reliability. In this paper, we summarize recent topics of IGBT and its analysis from the above points of view.

Low Power, High speed, Low leakage Floating Gate SRAM Cell using LECTOR Technique

Objective: Leakage power is the major concern of circuit designers in nano meter technology era. The objective of this work is to design a low leakage power floating gate MOS static random access memory. Methods/Statistical Analysis: The proposed design has been made using Floating Gate MOS (FGMOS) and Leakage Control Transistor (LECTOR) technique. FGMOS has been used in place of normal MOS on the conventional SRAM cell. In the LECTOR an NMOS transistor is incorporated between output and pull down the network and a PMOS transitor is incorporated between output and pull up a network. Findings: The SRAM cell has been designed and simulated in Cadence environment on 45 nm gpdk standard CMOS process technology. From the simulation results, it is found that LECTOR FGSRAM cell reduces 90.53% leakage power, 12% delay and 33.20% overall power consumption when compared to FGSRAM cell. A detailed comparison between FGSRAM cell and LECTOR FGSRAM cell performances has been reported during WRITE operation mode. Application/Improvements: It is found that hybrid technique should be added along with LECTOR to improve the parameters.

Exploring metalorganic chemical vapor deposition of Si-alloyed Al2O3 dielectrics using disilane

The alloying of Al2O3 films with Si is a promising route to improve gate dielectric properties in Si- and wide-bandgap- based MOS devices. Here we present a comprehensive investigation of alloyed film growth by metalorganic chemical vapor deposition (MOCVD) using trimethylaluminum, disilane, and oxygen precursors over a variety of temperature and flow conditions. Binary growth rates of Al2O3 and SiO2 were evaluated to explain the aggregate growth kinetics of Si-alloyed Al2O3 films, and refractive indices were used to monitor Si incorporation efficiencies. The temperature dependence of the reaction rate of disilane with oxygen was found to be similar to that of trimethylaluminum and oxygen, leading to well-behaved deposition behavior in the kinetic and mass-transport controlled growth regimes. Compositional predictability and stability was achieved over a wider growth space with disilane-based growths as compared to previous work, which used silane as the Si precursor instead. In situ (Al,Si)O/n-GaN MOS gate stacks were grown and showed increasing reduction of net positive fixed charges with higher Si composition.

Hydrogen gas detection using MOS capacitor sensor based on palladium nanoparticles-gate

In this study a palladium nanoparticles-gate MOS capacitor hydrogen sensor with Pd/SiO2/Si structure has been fabricated. The palladium nanoparticles by chemical method are synthesized and then characterized by transmission electron microscope (TEM), X-ray diffraction (XRD) and UV-VIS spectrum. Also, the preferred orientation and grain size of the palladium nanoparticles have been studied. Hydrogen absorption and desorption of the palladium nanoparticles at the low and high pressure and as function of time have been investigated. The sensing mechanism of the hydrogen detection by MOS capacitor sensor has been explained and theoretical and experimental results have been compared. At 287 K, compared to another Pd MOS capacitor hydrogen sensor and ultrathin Pd MOS capacitor, the palladium nanoparticles gate MOS capacitor showed much faster response and recovery speed. The time interval for reaching to 95% of the steady state signal magnitude (t95%) for 1% and 2% hydrogen in nitrogen were 2 s and 1.5 s respectively. The time interval for recovery transients from 95% to 10% of steady state signal magnitude (t10%) for 1% and 2% hydrogen in nitrogen were 10 s and 11 s respectively. The presented sensor illustrates a designing of hydrogen detectors with very fast response and recovery speed.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

&lt;em&gt;In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell&lt;/em&gt;