MOS Gate Stacks Research Articles

Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks

In this letter, low-temperature (480°C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and TaN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.

Interface characterization of metal-HfO2-InAs gate stacks using hard x-ray photoemission spectroscopy

MOS devices based on III-V semiconductors and thin high-k dielectric layers offer possibilities for improved transport properties. Here, we have studied the interface structure and chemical composition of realistic MOS gate stacks, consisting of a W or Pd metal film and a 6- or 12-nm-thick HfO2 layer deposited on InAs, with Hard X-ray Photoemission Spectroscopy. In and As signals from InAs buried more than 18 nm below the surface are clearly detected. The HfO2 layers are found to be homogeneous, and no influence of the top metal on the sharp InAs-HfO2 interface is observed. These results bridge the gap between conventional photoemission spectroscopy studies on various metal-free model samples with very thin dielectric layers and realistic MOS gate stacks.

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

One of the most critical issues for Ge/III-V MOSFETs is gate insulator formation. In this paper, we focus on viable Ge/III-V MOS gate stack technologies realizing the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). these requirements. As for Ge gate stacks, we present a ultrathin EOT Al2O3/GeOx/Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. (100) Ge pMOSFETs using GeOx/Ge MOS interfaces is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm2/Vs. As for InGaAs gate stacks, we show the impact of Al2O3 inter-layers on interface properties of HfO2/InGaAs MOS interfaces. The 1-nm-thick capacitance equivalent thickness (CET) in the HfO2/Al2O3/InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4e-2 A/cm2.

硬 X 線光電子分光法による深層状態分析

Hard X-ray photoelectron spectroscopy (HXPES) has developed to be used in wide ranges of solid state science and technology due to its much larger information depth comparing to the conventional X-ray photoelectron spectroscopy. It enabled to investigate buried layers as deep as more than 20 nm from the surface. Here in this article, various applications of HXPES to the deep layer investigations including chemical state profiling by takeoff angle dependence measurements and standing wave methods, intermixing analysis of metal multilayers, analysis of band bending at the semiconductor hetero interfaces, analysis of 2 dimensional carriers in strongly correlated materials interfaces, electronic structure observations at buried layers and their interfaces in devices. Laboratory HXPES system with monochromatic Cr Kα X-ray excitations is also introduced with its applications to Si MOS gate stack model samples including interface state spectroscopy by electric field application are also introduced.

InGaAs MOSゲートスタック形成と界面特性

InGaAs MOS gate stack formation and the MOS interface control technologies, which are mandatory for realizing high performance InGaAs MOSFETs, are addressed with an emphasis on our recent achievements. Al2O3/InGaAs MOS gate stacks formed by Atomic Layer Deposition (ALD) are known as one of the most superior InGaAs MOS interfaces. The experimental results of Al2O3/InGaAs, HfO2/InGaAs and HfO2/Al2O3/InGaAs interfaces are presented. It is found that 1-nm-capaciatance equivalent thickness can be realized by HfO2/Al2O3/InGaAs gate stacks. Also, semiconductor inteface buffer layers inserted between InGaAs channels and gate oxides are shown to be effective in further improving the channel mobility.

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/Ge CMOS integration. We have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. We have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin EOT by employing ALD Al2O3 and successive plasma oxidation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for InGaAs and Ge MOSFETs. By employing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

Modeling of the effective work function instability in metal/high-κ dielectric stacks

This paper discusses the effective work function instability in high-κ-based MOS gate stacks, which occurs after high temperature (1070 °C) processing. Theories which have been put forward to explain this effect are discussed and unified to a consistent phenomenological model. The Vfb roll-off effect is also discussed and can be described by the model.

High Mobility Channel Materials and Novel Devices for Scaling of Nanoelectronics beyond the Si Roadmap

AbstractHigh mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface. Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

Surface passivation technology for III–V semiconductor nanoelectronics

The present status and key issues of surface passivation technology for III–V surfaces are discussed in view of applications to emerging novel III–V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors’ group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy (MBE)-grown ultrathin Si layer inserted between III–V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented.

Impact of Device Layout and Annealing Process During the Passivation of Interface States in Presence of Silicon Nitride Layers

This paper reports the experimental evidence of anomalous electrical characteristics of large test structures for the characterization of both silicon-oxide-nitride-oxide-silicon (SONOS) and MOS gate stacks featuring nitride caps. The anomaly has been studied on devices featuring different layouts and it has been attributed to the property of silicon nitride layers to block the diffusion of hydrogen used for the passivation of the Si/SiO2 interface dangling bonds. Since the hydrogen passivation can occur only from the lateral sides of the device, our findings imply restrictions on the dimensions and on the layout of the test structures used to study the electrical properties of the gate stacks in SONOS or in large MOS devices featuring protective nitride caps.

Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks

In this work, we present a global methodology for an automatic and reliable extraction of VFB (Flat Band Voltage), EOT( Equivalent Oxide thickness) and leakage current at referenced biases (constant bias offsets from VFB or Vt, the threshold voltage) on advanced gate stacks. Parameter extraction is proposed as a post processing step after automatic measurement. A new reliable extraction method for VFB is presented and the interest of the methodology is highlighted on several experimental results.

Processing and evaluation of metal gate/high- κ/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO 2 and HfO 2 as high- κ dielectric

We evaluate various metal gate/high- κ/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO 2 and HfO 2 as the gate dielectric, respectively. The influence of the processing sequence – especially of the thermal annealing treatment – on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance–voltage behaviour (due to reduced interface-, and oxide charge density), current–voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO 2, at least within the process scheme we applied.

HfO 2 as gate dielectric on Ge: Interfaces and deposition techniques

To fabricate MOS gate stacks on Ge, one can choose from a multitude of metal oxides as dielectric material which can be deposited by many chemical or physical vapor deposition techniques. As a few typical examples, we will discuss here the results from atomic layer deposition (ALD), metal organic CVD (MOCVD) and molecular beam deposition (MBD) using HfO 2/Ge as materials model system. It appears that a completely interface layer free HfO 2/Ge combination can be made in MBD, but this results in very bad capacitors. The same bad result we find if HfGe y (Hf germanides) are formed like in the case of MOCVD on HF-dipped Ge. A GeO x interfacial layer appears to be indispensable (if no other passivating materials are applied), but the composition of this interfacial layer (as determined by XPS, TOFSIMS and MEIS) is determining for the C/ V quality. On the other hand, the presence of Ge in the HfO 2 layer is not the most important factor that can be responsible for poor C/ V, although it can still induce bumps in C/ V curves, especially in the form of germanates (Hf–O–Ge). We find that most of these interfacial GeO x layers are in fact sub-oxides, and that this could be (part of) the explanation for the high interfacial state densities. In conclusion, we find that the Ge surface preparation is determining for the gate stack quality, but it needs to be adapted to the specific deposition technique.

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

In this letter, a prototype of conductive atomic force microscope with enhanced electrical performance has been used to separately investigate the effect of the electrical stress on the SiO/sub 2/ and the HfO/sub 2/ layers of a high-/spl kappa/ gate stack. Charge trapping in HfO/sub 2/ native defects and degradation of both layers have been observed, depending on the stress level.

Processing Impact on Electrical Properties of Lanthanum Silicate Thin Films

AbstractThe consequence of tungsten metal purity on the electrical properties of an annealed MOS gate stack with a lanthanum silicate gate dielectric has been investigated. Optimization of the electrical and physical properties of a device with any given dielectric requires the proper choice of metal gate electrode and capping layer. This study is intended to show the importance of tungsten processing optimization and subsequent effects on the equivalent oxide thickness, fixed charge, and density of interface states of La-Si-O gate dielectric MIS devices. In the experiment, La-Si-O films of physical thickness of 1.6 nm were deposited on a Si substrate, subsequently depositing TaN as the gate electrode and W as a capping layer. A post metallization anneal in flowing nitrogen at 1000°C for short times resulted in widely different measured properties of the MIS devices, dependent on the quality of the tungsten deposited. XRD and SIMS profiles of the gate stacks showed a clear relationship between concentration of oxygen and processing of the tungsten. A 1000°C, 10 sec anneal resulted in an EOT change from 1.1 nm to 2.2 nm on gate stacks with low and high oxygen concentration in the tungsten, respectively. Defect densities decreased with increased anneal temperature and time, and annealing with low oxygen-concentration tungsten resulted in higher effective fixed charge. SIMS data suggests that oxygen in the tungsten diffuses to the Si/La-Si-O interface through the TaN electrode, resulting in the observed differences in the defect densities and EOT.

Pre- and post-BD electrical conduction of stressed HfO 2/SiO 2 MOS gate stacks observed at the nanoscale

In this work, the electrical properties of fresh and stressed HfO 2/SiO 2 gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO 2 and the HfO 2 layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.

Electrical characterization ofhigh-dielectric-constant/SiO2 metal–oxide–semiconductor gate stacks by a conductive atomic force microscope

A conductive atomic force microscope (CAFM) has been used to study, at the nanometrescale, the dependence of the electrical behaviour on the post-deposition annealing temperature(TA) and the dielectric reliability of ultrathinhigh-dielectric-constant/SiO2 MOS gate stacks. It has been observed that for high enoughTA the conduction becomes more inhomogeneous, leading to the formation of leaky spots thatcould be a problem for the integration of these layers in a standard CMOS microelectronicprocess. The CAFM has also revealed that the values of some parameters related to thedielectric reliability, such as the area of the breakdown spot (i.e. a region that haslost its insulating properties owing to electrical stress), are of the same order forSiO2 layers andhigh-dielectric-constant/SiO2 stacks. Moreover, different conduction regimes, which cannot be detected by standardelectrical characterization techniques, have been observed.

Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO/sub 2/ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO/sub 2/, Si/sub 3/N/sub 4/, ZrO/sub 2/, and HfO/sub 2/ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-/spl kappa/ gate dielectrics.

Smooth amorphous silicon deposition on silicon dioxide with high deposition rates by rapid thermal chemical vapor deposition using disilane

In this paper, we report amorphous silicon (α-Si) deposition on SiO 2 by rapid thermal chemical vapor deposition for the first time at rates compatible with single wafer manufacturing. Depositions were performed using 10% Si 2H 6 in H 2 at 1 Torr in the temperature range 550 to 750 °C. Very high deposition rates are achieved and these rates range from 45 nm/min to as high as 650 nm/min. Analysis of the films by transmission electron microscopy indicates α-Si deposition at temperatures below approximately 600 °C. At temperatures around 625 °C, films with a bilayer amorphous-polycrystalline composite microstructure were obtained which was attributed to a deposition rate greater than the crystallization rate. Analysis of these low temperature films by atomic force microscopy yields rms roughness values, in general, that are less than 1.5 nm and as low as 0.3 nm. The smoothness of the films is comparable to the best α-Si films obtained by conventional low pressure chemical vapor deposition using SiH 4 or Si 2H 6. In summary, by using an efficient source gas, we are able to deposit very smooth Si films by rapid thermal chemical vapor deposition which we believe is a viable option for high quality MOS gate stack formation in a single wafer manufacturing environment.