MOS Capacitors Research Articles

Characterization of thin Al2O3/SiO2 dielectric stack for CMOS transistors

This paper systematically investigates the electrical properties of thin Al2O3/SiO2 (with a target equivalent oxide thickness of 4.9 nm) as gate dielectric stack in the metal–oxide–semiconductor (MOS) capacitor. Different deposition techniques, i.e. thermal oxidation, thermal atomic layer deposition, and plasma-enhanced atomic layer deposition, are employed in the fabrication of MOS capacitors. The second derivative, Terman and conductance methods are used to extract the fixed oxide charges and interface trap densities in the MOS capacitors. Our results demonstrate that the Al2O3/SiO2 stack presents better performance in terms of negative fixed oxide charges and low interface trap density compared with the single-layer SiO2 with the similar equivalent oxide thickness about 3.9 nm. Furthermore, to evaluate the reliability of the Al2O3/SiO2 gate dielectric stack, the leakage current is analyzed. Contributions from Pool-Frenkel emission, trap-assisted tunneling, and Fowler-Nordheim mechanisms to the leakage current are detailed. Our results indicate that Al2O3/SiO2 gate dielectric stacks fabricated by plasma-enhanced atomic layer deposition Al2O3 and thermal SiO2 feature the lowest leakage current.

A new high frequency MOS-C TOETQO employing DXCCTA

ABSTRACT This research paper reports a high frequency Third Order Electronically Tunable Quadrature Oscillator (TOETQO) using an active element termed as Dual-X Current Conveyor Transconductor Amplifier (DXCCTA) in which active element MOS and passive Capacitor (C) contribute the implementation performance of the proposed design as MOS-C TOETQO. Due to the presence of DXCCTA with active grounded capacitor and MOS-based resistor, the proposed quadrature oscillator facilitates a suitable design for integrated circuits (ICs). The proposed TOETQO circuit produces current as well as voltage outputs simultaneously. Moreover, the non-ideal analysis of the proposed oscillator circuit is also included. The proposed design shows a good agreement for the oscillation criteria due to the acceptable limit of %THD and gives the variation in frequency of oscillation (up to MHz) values with respect to bias current. Moreover, by keeping the bias current constant, frequency of oscillation can also be electronically tuned independently by varying the values of resistor. Finally, Cadence simulation results are depicted to verify the theoretical analyses and practical feasibility of proposed TOETQO design is also well verified with experimental set up by using IC AD844 and CA3080. A fair comparison of the proposed quadrature oscillator with existing literatures is also tabulated.

Demonstration of a 17 × 25 Gb/s Heterogeneous III-V/Si DWDM Transmitter based on (De-) Interleaved Quantum Dot Optical Frequency Combs

We discuss the design and demonstration of a space and dense wavelength division multiplexed heterogeneous III-V/Si transmitter based on a single multi-wavelength quantum dot laser source and ultra-power-efficient metal-oxide-semiconductor capacitor (MOSCAP) (de-)interleaver. This paper begins by introducing a transceiver architecture capable of > 1 Tb/s transmission with < 1.5 pJ/bit power consumption, followed by a detailed discussion of the heterogeneous laser source and (de-)interleaver. The O-band quantum dot laser, based on a compound cavity design, has a FSR ∼ 64 GHz with a 1σ variation of ∼ 1.08 GHz and a measured relative intensity noise (RIN) of ∼ -144 dB/Hz for the largest comb peak. The single-ring-assisted asymmetric Mach-Zehnder interferometer (1-RAMZI) MOSCAP (de-)interleaver exhibit cross-talk (XT) levels down to -27 dB for tuning powers of 10.0 nW. Finally, to the best of our knowledge, we have demonstrated for the first time, a simultaneous wavelength and space division multiplexed transmitter fabricated on a heterogeneous III-V-on-silicon platform. Experiments show (de-)interleaved 17 optical comb lines, each modulated at 25 Gb/s non-return-to-zero (NRZ) for an aggregate bandwidth of 425 Gb/s.

Active inductor based low phase noise voltage controlled oscillator

This paper proposed a fully MOS-based voltage-controlled oscillator (VCO) with tuning range and low phase noise, replacing the most often used NMOS-based inductor-capacitor tank arranged in cross-coupled topology with a high-Q active inductor. This study mainly focuses on VCO design using a MOS-based active inductor and is implemented and verified using UMC 180nm CMOS technology. The proposed VCO is resistorless and consists of an active inductor, two MOS capacitors, and the buffer circuits. The fundamental principle of this MOS-based VCO concept is to use MOS based inductor to replace the passive inductor, which is an active inductor that gives less area and low power usage. At 1 MHz frequency offset, the phase noise achieved by this proposed configuration is -102.78dBc/Hz. In the proposed VCO architecture, the frequency tuning range is 0.5GHz to 1.7GHz. This VCO design can accomplish this acceptable tuning range by altering the regulating voltage from 0.7V to 1.8V. This suggested architecture of proposed VCO design has the power consumption of 9mW with a 1.8V supply voltage. The suggested VCO has been shown to be a good fit for low-power RF circuit applications while preserving acceptable performance metrics.

Fabrication and Characterization of 2-Bit per Capacitor as Functional Structures for Physical Unclonable Function Circuits

Currently, security issues for semiconductor chips are counterfeiting and night shift problems. These factors might lead to insecure supply chains in the automotive industry. This can be avoided by using coating Physical Unclonable Functions (PUFs). The coating can be applied to every semiconductor chip in order to create a unique fingerprint. In this work, a 2-bit key per capacitor for Physical Unclonable Functions is presented for the first time. For this reason, 49 chips on a wafer with 195 metal oxide semiconductor (MOS) capacitors were fabricated. A large and random fluctuation of the capacitances was achieved by using a self-developed layer, which consisted of aluminum particles and spin-on glass. Due to the random variation in size and change in distribution of the particles, the fluctuation of capacitance varied from chip to chip and from wafer to wafer. The achieved large range in capacitance was used to create a 390-bit string out of 195 capacitors. Although the length of the bit string was doubled, the area of the structure remained constant. This led to a more secure PUF with a low error rate of 0.21% and an inter-chip Hamming distance (HD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inter</sub> ) of 49%.

SiC/SiO2 interface properties formed by low-temperature ozone re-oxidation annealing

We propose an ECR ozone plasma re-oxidation annealing (ROA) method that can introduce high-concentration and high-reactivity O atoms to eliminate defects near the SiC/SiO2 interface with low temperature (400 °C). This method can more effectively improve the electrical performance of SiC MOS capacitors compared with other ROA methods, including O2, O3 and O2 plasma ROA methods. Secondary ion mass spectroscopy (SIMS), atomic force microscope (AFM) and X-ray photoelectron spectroscopy (XPS) are performed. Results indicate that the O3P-ROA can evidently re-oxidize near-interface defects, which optimize near-interface properties, including the elemental distribution of the near-interface region and the morphology of the SiC/SiO2 interface. In addition, the effects of temperature and oxygen element on near-interface properties of SiC MOS capacitors are discussed in this paper.

Impact of Substrate Biasing During AlN Growth by PEALD on Al2O3/AlN/GaN MOS Capacitors

AbstractIn this article, the role of the substrate biasing during the passivation of GaN with AlN deposited by plasma enhanced atomic layer deposition (PEALD) is investigated. In addition to a commonly used remote inductively‐coupled plasma source, the PEALD reactor is equipped with another power supply allowing the substrate to be biased and to adjust the ion energy impinging on the substrate surface. The presence is reported of a narrow bias window where the GaN passivation is significantly improved compared to a standard AlN film deposited without bias. It is found that the AlN film quality is enhanced and the crystallographic structure changes from a well‐ordered epitaxial relationship with the GaN substrate to textured films when applying a bias. Finally, the capacitance–voltage characteristics (C–V) of Al2O3/n‐GaN and Al2O3/AlN/n‐GaN metal‐oxide‐semiconductor (MOS) capacitors are also studied. It is shown that the addition of an AlN interlayer deposited with the appropriate bias is essential to positively shift the flatband voltage of the C–V characteristics while preserving high AlN/n‐GaN interface quality. Therefore, the GaN passivation with AlN deposited using substrate biasing provides a promising pathway towards the manufacturing of normally‐off MOS‐channel high electron mobility transistors.

Building resistive switching memory having super-steep switching slope with in-plane boron nitride

The two-dimensional hexagonal boron nitride (h-BN) has been used as resistive switching (RS) material for memory due to its insulation, good thermal conductivity and excellent thermal/chemical stability. A typical h-BN based RS memory employs a metal-insulator-metal vertical structure, in which metal ions pass through the h-BN layers to realize the transition from high resistance state to low resistance state. Alternatively, just like the horizontal structure widely used in the traditional MOS capacitor based memory, the performance of in-plane h-BN memory should also be evaluated to determine its potential applications. As consequence, a horizontal structured resistive memory has been designed in this work by forming freestanding h-BN across Ag nanogap, where the two-dimensional h-BN favored in-plane transport of metal ions to emphasize the RS behavior. As a result, the memory devices showed switching slope down to 0.25 mV dec−1, ON/OFF ratio up to 108, SET current down to pA and SET voltage down to 180 mV.

Miniature, highly sensitive MOSCAP ring modulators in co-optimized electronic-photonic CMOS

Convergence of high-performance silicon photonics and electronics, monolithically integrated in state-of-the-art CMOS platforms, is the holy grail for enabling the ultimate efficiencies, performance, and scaling of electronic-photonic systems-on-chip. It requires the emergence of platforms that combine state-of-the-art RF transistors with optimized silicon photonics, and a generation of photonic device technology with ultralow energies, increased operating spectrum, and the elimination of power-hungry thermal tuning. In this paper, in a co-optimized monolithic electronics-photonics platform (GlobalFoundries 45CLO), we turn the metal-oxide-semiconductor (MOS) field-effect transistor’s basic structure into a novel, highly efficient MOS capacitor ring modulator. It has the smallest ring cavity (1.5 μm radius), largest corresponding spur-free free spectral range ( FSR = 8.5 THz ), and record 30 GHz/V shift efficiency in the O-band among silicon modulators demonstrated to date. With 1 V pp RF drive, we show an open optical eye while electro-optically tuning the modulator to track over 400 pm (69 GHz) change in the laser wavelength (using 2.5 V DC range). A 90 GHz maximum electro-optic resonance shift is demonstrated with under 40 nW of power, providing a strong nonthermal tuning mechanism in a CMOS photonics platform. The modulator has a separately optimized body layer but shares the gate device layer and the gate oxide with 45 nm transistors, while meeting all CMOS manufacturability design rules. This type of convergent evolution of electronics and photonics may be the future of platforms for high-performance systems-on-chip.

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer.

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

Unraveling the Mechanism of Remote Scavenging Effect at the InP/Al2O3 Interface Induced by Titanium Layer

AbstractLow interface oxide concentration is desired for III‐V semiconductor/high k dielectrics stacks to get high‐performance devices. The remote scavenging effect is observed upon Ti metal deposition on the InP/Al2O3 system, characterized by in situ angle resolved X‐ray photoelectron spectroscopy and time‐of‐flight secondary ion mass spectrometry, as well as ex situ cross‐sectional transmission electron microscopy. The mechanism is investigated by O18 tracing. Two mechanisms are proposed for this remote scavenging effect. The impact of this remote scavenging effect is studied by metal oxide semiconductor (MOS) capacitors fabrication and characterization. This work sheds light on InP‐based MOS devices.

Synergistic effects in MOS capacitors with an Au/HfO2–SiO2/Si structure irradiated with neutron and gamma ray

The properties of oxide trapped charges and interface state density in the metal oxide semiconductor (MOS) capacitors with an Au/HfO2–SiO2/Si structure were investigated under irradiation of 14 MeV neutron and 60Co gamma-ray. In the mixed neutron and gamma irradiation environment, the formation of the oxide trapped charges in the HfO2–SiO2 layer is determined by the total deposited ionization energy, i.e. the sum of ionization energy deposition of the neutrons and the accompanying gamma rays, while the influence of the displacement damage caused by 14 MeV neutrons can be ignored. The interface state density depends not only on the ionizing energy loss (IEL) but also the non-IEL (NIEL), and NIEL plays a major role below the critical neutron fluence of 4.5 × 1012 n cm−2. The synergistic effect of the interface state is observed increases with energy deposition in the oxide at lower fluences, while decreasing above the critical fluence. These results confirm the existence of the synergistic effect of neutron and gamma irradiation in damaging HfO2 MOS devices.

Radio frequency power controlled [formula omitted] crystal phase transition from monoclinic to cubic

Rare earth oxides such as Gadolinia (Gd2O3) are extensively explored for buried oxide (BOX) application as a replacement for silicon dioxide (SiO2) in silicon-on-insulator (SOI) substrates. Of all the proposed methods, molecular-beam-epitaxy-based techniques have shown perfectly single-crystalline growth of Gd2O3. We present a radio frequency (RF) magnetron sputter based low-cost technique to grow single-crystalline Gd2O3 on Si (111) substrate. We show a gradual phase transition of the Gd2O3 layer from monoclinic to cubic by engineering the Gd2O3 deposition rate–i.e., tuning the RF power. We present a comparison amongst three samples as follows: (a) monoclinic; (b) monoclinic+cubic; (c) cubic at three different RF powers keeping the rest of the process conditions such as chamber pressure, Argon flow rate, etc., fixed. Further, we present a detailed structural characterization of all the three samples using a high-resolution X-ray diffraction system. Using the ω−2θ and pole-figure measurements we show a highly textured monoclinic Gd2O3 layer formation with (-402) crystal orientation in experiment (a). In experiment (c) we show phase transition of Gd2O3 from monoclinic to cubic by tuning the RF power. Finally, with experiment (b), we demonstrate that the aforementioned phase transition is a gradual phenomenon by highlighting a coexistence of both the monoclinic and cubic phases at an intermediate RF power. To ensure the electrical characteristics of the grown dielectric we present a metal oxide semiconductor capacitor structure fabrication for the monoclinic and the cubic Gd2O3 layers and benchmark the interface trap density, and dielectric constant against state-of-the-art literature. We show an improvement in the interface trap density, and reduction in the hysteresis from monoclinic to cubic phase transition due to an improved epitaxial relation between cubic Gd2O3 and Si(111) substrate. Such low-cost methods of growing single-crystalline Gd2O3 layer has the potential to replace the SiO2 BOX layer, and significantly bring down the manufacturing cost of the existing SOI wafer technology.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

Transport mechanism in O-terminated diamond/ZrO2 based MOSCAPs

Metal Oxide Semiconductor capacitors were fabricated using p-type O-terminated (001) diamond and zirconium dioxide deposited by atomic layer deposition at low temperature (100 °C). X-ray diffraction and transmission electron microscopy evidence monoclinic structure and polycrystalline nature of the oxide layer. I-V, CV and CF experiments have been performed in a large frequency range, i.e. from 1 Hz to 1 MHz, in order to analyse the electrical properties of the metal/dielectric/diamond stack. The presence of charges in the oxide and interface states induces a flat-band voltage shift in the CV curve and a strong Fermi level pinning effect. A leakage current mechanism considering the correlation of the microstructural characterization and the electrical response is proposed.

Large-scale and energy-efficient tensorized optical neural networks on III–V-on-silicon MOSCAP platform

This paper proposes a large-scale, energy-efficient, high-throughput, and compact tensorized optical neural network (TONN) exploiting the tensor-train decomposition architecture on an integrated III–V-on-silicon metal–oxide–semiconductor capacitor (MOSCAP) platform. The proposed TONN architecture is scalable to 1024 × 1024 synapses and beyond, which is extremely difficult for conventional integrated ONN architectures by using cascaded multi-wavelength small-radix (e.g., 8 × 8) tensor cores. Simulation experiments show that the proposed TONN uses 79× fewer Mach–Zehnder interferometers (MZIs) and 5.2× fewer cascaded stages of MZIs compared with the conventional ONN while maintaining a &amp;gt;95% training accuracy for Modified National Institute of Standards and Technology handwritten digit classification tasks. Furthermore, with the proven heterogeneous III–V-on-silicon MOSCAP platform, our proposed TONN can improve the footprint-energy efficiency by a factor of 1.4 × 104 compared with digital electronics artificial neural network (ANN) hardware and a factor of 2.9 × 102 compared with silicon photonic and phase-change material technologies. Thus, this paper points out the road map of implementing large-scale ONNs with a similar number of synapses and superior energy efficiency compared to electronic ANNs.

Electrical and Optical Characteristics of SSI-LED Made from Capacitor Containing Tri-Layer WOx Embedded Zr-Doped HfOx Gate Dielectric

Solid-state incandescent light emitting devices made from MOS capacitors with the WOx embedded Zr-doped HfOx gate dielectric were characterized for electrical and optical characteristics. Devices made from capacitors containing Zr-doped HfOx and WOx, gate dielectrics were also fabricated for comparison. The device with the WOx embedded gate dielectric layer had electrical and light emitting characteristics between that with WOx gate dielectric layer and that with the Zr-doped HfOx but no WOx embedded gate dielectric layer. The difference can be explained by the nano-resistor formation process and the content of the high emissivity W in the nano-resistor. The device made from the WOx embedded Zr-doped HfOx gate dielectric MOS capacitor is applicable to areas where uniform emission of warm white light is required.

Improved Tradeoff Between Subthreshold Swing and Hysteresis for MoS2Negative-Capacitance FETs by Optimizing Gate-Stack of Hf1−xZrxO2/Al2O3

MoS₂ negative-capacitance field-effect transistors (NCFETs) with a gate-stack of Hf₁₋ₓZrₓO₂/Al₂O₃ are fabricated, and the effects of the Zr content and the thickness of the stacked gate on electrical performance of the devices are investigated. It is found that a large improvement of device performance can be achieved by optimizing these parameters, e.g., using 6-nm Hf $_{0.5}$ Zr $_{0.5}$ O₂ (Zr content of 50%) as a ferroelectric layer and 2-nm Al₂O₃ as a matching layer, the relevant MoS₂ NCFET exhibits the excellent electrical characteristics: a low subthreshold swing (SS) of 31.4 mV/dec, a smaller counterclockwise hysteresis of ~75 mV, and a high on/off current ratio of 3.26 x 10⁶. The involved mechanisms lie in that: 1) an enhanced remnant polarization leads to low SS and 2) changing the thickness of the Hf₁₋ₓZrₓO₂ and Al₂O₃ can adjust the magnitude of ferroelectric capacitance and MOS capacitance to realize a reasonable match between both.

A promising method to improve the bias-stress and biased-radiation-stress stabilities of solution-processed AlOx thin films

The effects of hydrogen peroxide (H2O2) on the device properties and stabilities of solution-processed AlOx metal-oxide-semiconductor capacitors (MOSCAPs) were investigated. It is demonstrated that H2O2 is a strong oxidizer to decompose precursor residuals, reduce oxygen vacancy (Vo) and defects density of solution-processed AlOx thin films. The interface quality and the bias-stress (BS) stability of AlOx MOSCAPs were improved by employing H2O2. Furthermore, through carrying out on-site measurements, 7.5 M H2O2 AlOx MOSCAPs exhibited ignorable radiation-induced oxide traps and interface traps under biased-radiation-stress (BRS) with a total dose up to 42 Gy (SiO2). The 7.5 M H2O2 AlOx MOSCAPs also demonstrate the ability to recover under radiation after the bias was interrupted. The reduced number of Vo and high AlOx concentration of 7.5 M H2O2 AlOx could suppress the radiation-induced trapping/de-trapping behavior among the AlOx bulk and the breaking of Si–H bonds at the AlOx/Si interface. Besides, through biased-illumination-stress (BIS) measurements, the breaking of Si–H bonds under negative biased-radiation-stress (NBRS) was further proved. The results demonstrate that employing H2O2 in the solution-process is simple and effective; it has significant potential to improve the stabilities of large-area electronics for nuclear and aerospace applications.

Influence of substrate temperature on optical, structural and dielectric properties of TiO2 thin films prepared by spray pyrolysis technique

Titanium dioxide (TiO2) thin films are prepared on various substrates like glass and silicon wafers by spray pyrolysis method. The spray solution is prepared by dissolving titanium-tetra isopropoxide (TTIP) in ethanol. Optical, structural and dielectric properties of these films are studied by the transmittance spectra, X-ray diffraction (XRD), atomic force microscopy (AFM), capacitance–voltage (C-V) characteristics, respectively. TiO2 metal oxide semiconductor (MOS) capacitors are fabricated using TiO2 as a dielectric medium. C-V plots are analyzed to determine the dielectric constant (εr) of TiO2 film. The dependance of εr of the TiO2 films with the substrate temperature has been investigated.