Moore's Era Research Articles

Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution.

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

Study on the Manufacturability of XDFOI Package with Organic RDLs (XDFOI-O)

The concept of chiplet has been proposed in the post Moore era, while how to achieve the layout of multiple chips of different processes and sizes in the manufacturing process is a coming problem that needs to be considered. Different layouts may significantly affect the manufacturability during the packaging process. Prospective finite element analysis (FEA) can evaluate various layouts by optimizing the layout and increasing the placement of dummy chips as stiffeners, thereby selecting the best layout and combination method. In addition, the characteristic of chiplet packaging is that multiple chips may come from different sources, such as different foundries, processes, sizes, or even thicknesses. This really poses challenges to the subsequent flip chip and wafer thinning process for leveling the total package. It is necessary to confirm the evaluation of the impact of chips with different thicknesses and underfill coverage in the process, so as to ensure the consistency in processing and improve the yield of packages.

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.

Addressing Advanced IC Substrate Deformation and Pattern Distortion Using an Extremely Large Exposure Field Fine Fine-Resolution Lithography System

The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75mm x 75mm to 175mm x 175mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges. For starters, package sizes are expected to grow significantly due to the number of components making up each integrated package. The problem: these significantly larger packages would typically require multiple exposure shots to complete the lithography steps for the package. Furthermore, the process of adding multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate. Formation changes experienced by the panel, as a result of thermal, high-pressure and other fan-out processes, shift the design location from its nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. And then there is the matter of tightening resolution requirements. RDL layers in advanced integrated circuit substrates (AICS) will require a resolution of 3µm and will eventually move toward a resolution of 1µm. To address these challenges, and better enable the heterogenous integration process, an extremely large exposure field, fine-resolution lithography solution was proposed to enable packages over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical dimension uniformity requirements for these packages. In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use an extremely large exposure field, fine-resolution lithography system to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field, fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.

Self-Rolled-Up Ultrathin Single-Crystalline Silicon Nanomembranes for On-Chip Tubular Polarization Photodetectors.

Freestanding single-crystalline nanomembranes and their assembly have broad application potential in photodetectors for integrated chips. However, the release and self-assembly process of single-crystalline semiconductor nanomembranes still remains a great challenge in on-chip processing and functional integration, and photodetectors based on nanomembrane always suffer from limited absorption of nanoscale thickness. Here, a non-destructive releasing and rolling process is employed to prepare tubular photodetectors based on freestanding single-crystalline Si nanomembranes. Spontaneous release and self-assembly are achieved by residual strain introduced by lattice mismatch at the epitaxial interface of Si and Ge, and the intrinsic stress and strain distributions in self-rolled-up Si nanomembranes are analyzed experimentally and computationally. The advantages of light trapping and wide-angle optical coupling are realized by tubular geometry. This Si microtube device achieves reliable Ohmic contact and exhibits a photoresponsivity of over 330mA W-1 , a response time of 370 µs, and a light incident detection angle range of over 120°. Furthermore, the microtubular structure shows a distinct polarization angle-dependent light absorption, with a dichroic ratio of 1.24 achieved at 940nm. The proposed Si-based microtubes provide new possibilities for the construction of multifunctional chips for integrated circuit ecosystems in the More than Moore era.

A QCA placement and routing algorithm based on the SA algorithm

ABSTRACT In the Beyond Moore era, QCA (Quantum-dot Cellular Automata) has been widely studied because of its low power consumption and high device concentration. As the core of chip design, EDA technology has become an indispensable step in QCA research. It refers to the use of computer-aided design software to complete large-scale circuit function design, logic synthesis, placement and routing, design rule check and other processes. In the present study, there are still many defects in QCA placement and routing. The main problems it faces are low success rate, too large area and too many cross lines. To address these problems, our team had proposed a hybrid strategy based on the genetic algorithm and the improved A-star algorithm. But the running time of the previously proposed algorithm is not satisfying, besides it lacks self-adaption feature which is important as the problem size varies among different circuits. This paper replaces the genetic algorithm with a simulated annealing algorithm, and introduces a self-adaption strategy to better accommodate different circuit sizes. Experimental results show that the new algorithm combination possesses a higher success rate, lower running time and more intelligent adaption ability.

Comparative coherence between layered and traditional semiconductors: unique opportunities for heterogeneous integration

Abstract As Moore’s law deteriorates, the research and development of new materials system are crucial for transitioning into the post Moore era. Traditional semiconductor materials, such as silicon, have served as the cornerstone of modern technologies for over half a century. This has been due to extensive research and engineering on new techniques to continuously enrich silicon-based materials system and, subsequently, to develop better performed silicon-based devices. Meanwhile, in the emerging post Moore era, layered semiconductor materials, such as transition metal dichalcogenides (TMDs), have garnered considerable research interest due to their unique electronic and optoelectronic properties, which hold great promise for powering the new era of next generation electronics. As a result, techniques for engineering the properties of layered semiconductors have expanded the possibilities of layered semiconductor-based devices. However, there remain significant limitations in the synthesis and engineering of layered semiconductors, impeding the utilization of layered semiconductor-based devices for mass applications. As a practical alternative, heterogeneous integration between layered and traditional semiconductors provides valuable opportunities to combine the distinctive properties of layered semiconductors with well-developed traditional semiconductors materials system. Here, we provide an overview of the comparative coherence between layered and traditional semiconductors, starting with TMDs as the representation of layered semiconductors. We highlight the meaningful opportunities presented by the heterogeneous integration of layered semiconductors with traditional semiconductors, representing an optimal strategy poised to propel the emerging semiconductor research community and chip industry towards unprecedented advancements in the coming decades.

Recent Advances in Layered Two‐Dimensional Ferroelectrics from Material to Device

AbstractWith the advent of the post Moore era, modern electronics require further device miniaturization of all electronic components, particularly ferroelectric memories, due to the need for massive data storage. This demand stimulates the exploration of robust switchable ferroelectric polarizations at the atomic scale. In this scenario, van der Waals ferroelectrics have recently gained increasing attention because of their stable layered structure at nanometer thickness, offering the opportunity to realize two‐dimensional ferroelectricity that is long‐sought in conventional thin film ferroelectrics. In this review, recent advancements are summarized in layered ferroelectrics with highlights of the fundamentals of intrinsic two‐dimensional ferroelectricity, the emergence of artificial stacking ferroelectricity, and related protype devices with exotic functions. In addition, the unique polarization control in van der Waals ferroelectrics is discussed. Although great challenges remain unsolved, these studies undoubtedly advance the integration of 2D ferroelectrics in electronics.

Evolution between Volatile and Nonvolatile Resistive Switching Behaviors in Ag/TiOx/CeOy/F-Doped SnO2 Nanostructure-Based Memristor Devices for Information Processing Applications

It is well known that higher requirements have been put forward for the computing efficiency and storage speed of the data processing of memory devices in the post Moore era. In particular, if a memory device with multiple physical characteristics can be developed, it will play an important role in realizing multifunctional applications of electronic systems. Here, a nanoscale memristor device with a Ag/TiOx/CeOy/F-doped SnO2 structure was prepared, which shows many interesting physical phenomena with the changing of the applied voltage. In the low-voltage region (<1.5 V), the device presents a volatile property, while it presents a nonvolatile behavior when a higher voltage (>2 V) was applied. Interestingly, the non-zero-crossing current–voltage (I–V) hysteresis behavior caused by the internal electromotive force appears in the voltage region of 0.5–1 V. Furthermore, as the applied voltage increases, the device gradually displays ideal memristor behavior and exhibits the standard resistance switching characteristic accompanied by the negative differential resistance effect in the region of 3.5–4.0 V. Therefore, this nanoscale device with multiple physical properties opens up a promising way for understanding the emerging physical phenomena, and it will be expected to become a potential candidate for the next generation of multifunctional electronic devices.

The Third generation semiconductor materials and devices in the post Moore era: Applications and progress

The Third generation semiconductor materials and devices in the post Moore era: Applications and progress

Covering the Broad Spectrum of Intelligent Systems: From Neuromorphic Engineering to Robotics

Covering the Broad Spectrum of Intelligent Systems: From Neuromorphic Engineering to Robotics

Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.

Rebooting Computing in Post Moore Era

Rebooting Computing in Post Moore Era

Integrated fabrication and ferroelectric domain adjustment of lithium niobate single crystal films based on silicon substrate

In the post Moore era, as the size miniaturization approaches limit of the devices, silicon-based sensors cannot meet the requirements of micro/nano sensing with small size and high precision. The piezoelectric sensor based on lithium niobate (LN) single crystal thin film has excellent electromechanical property, photoelectric property, piezoelectric property, which can realize high precision sensing at small size. In our work, 4-inch silicon-based LN single crystal thin film was prepared based on low-temperature bonding technology and chemical mechanical polishing (CMP) method. The oxygen plasma treatment was adopted for increasing the surface hydrophilia to enhance the bonding strength. Grinding parameters under different film thickness were determined by experiments. The parameters of the film was characterized by scanning electron microscope (SEM) with a thickness of 6.294 μm and by atomic force microscope (AFM) obtained the surface roughness is 585 pm. The x-ray diffraction (XRD) test showed that the CMP process could release the compressive stress caused by the bonding, thus obtaining high quality LN single crystal films. The prepared films are polarized and the domain walls can be clearly observed by piezoresponse force microscopy (PFM). It provides a more comprehensive way to prepare ferroelectric domain devices.

Nonvolatile Logic and Ternary Content-Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors.

Hardware realization of in-memory computing for efficient data-intensive computation is regarded as a promising paradigm beyond the Moore era. However, to realize such functions, the device structure using traditional Si complementary metal-oxide-semiconductor (CMOS) technology is complex with a large footprint. 2D material-based heterostructures have a unique advantage to build versatile logic functions based on novel heterostructures with simplified device footprint and low power. Here, by adopting the charge-trapping mechanism between a black phosphorus (BP) channel and a phosphorus oxide (POx ) layer, a nonvolatile CMOS logic circuit based on 2D BP and rhenium disulfide (ReS2 ) with a high voltage gain of ≈275 is realized with a persistent hysteresis window. A Schmidt-like flip-flop using only two transistors is also demonstrated, with far fewer transistor numbers than the conventional silicon counterpart, which usually requires six transistors. Furthermore, four-transistor (4T) nonvolatile ternary content-addressable memory (nvTCAM) cells are demonstrated with far fewer transistors for parallel data search. The nvTCAM cells exhibit high resistance ratios (Rratio ) up to ≈103 between match and mismatch states with zero standby power thanks to the nonvolatility of the BP transistors. This back-end-of-line compatible nvTCAM shows advantages over other structures with reduced complexity and thermal budget.

Advances and Frontiers in Single-Walled Carbon Nanotube Electronics.

Single‐walled carbon nanotubes (SWCNTs) have been considered as one of the most promising electronic materials for the next‐generation electronics in the more Moore era. Sub‐10 nm SWCNT‐field effect transistors (FETs) have been realized with several performances exceeding those of Si‐based FETs at the same feature size. Several industrial initiatives have attempted to implement SWCNT electronics in integrated circuit (IC) chips. Here, the recent advances in SWCNT electronics are reviewed from in‐depth understanding of the fundamental electronic structures, the carrier transport mechanisms, and the metal/SWCNT contact properties. In particular, the subthreshold switching properties are highlighted for low‐power, energy‐efficient device operations. State‐of‐the‐art low‐power SWCNT‐based electronics and the key strategies to realize low‐voltage and low‐power operations are outlined. Finally, the essential challenges and prospects from the material preparation, device fabrication, and large‐scale ICs integration for future SWCNT‐based electronics are foregrounded.

Nonlinearity in Memristors for Neuromorphic Dynamic Systems

As semiconductor technology enters the more than Moore era, there exists an apparent contradiction between the rapidly growing demands for data processing and the visible inefficiency rooted in traditional computing architecture. Neuromorphic systems hold great prospects in enabling a new generation of computing paradigm that can address this issue, which demands device components with rich dynamics and nonlinearity. Herein, the nonlinearity in memristive devices and their application in building neuromorphic dynamic systems are reviewed. The internal mechanisms that endow memristive devices with nonlinearity and rich dynamics are reviewed and subsequently the nonlinear spiking neurons that are implemented utilizing the physical processes in memristors are shown. Typical examples on neuromorphic dynamic systems based on nonlinear memristors are summarized, including memristive reservoir, memristive oscillatory neural network, and memristive chaotic computing. Finally, an outlook in the development of neuromorphic dynamic systems is given.

System-Theoretic Methods for Designing Bio-Inspired Mem-Computing Memristor Cellular Nonlinear Networks

The introduction of nano-memristors in electronics may allow to boost the performance of integrated circuits beyond the Moore era, especially in view of their extraordinary capability to process and store data in the very same physical volume. However, recurring to nonlinear system theory is absolutely necessary for the development of a systematic approach to memristive circuit design. In fact, the application of linear system-theoretic techniques is not suitable to explore thoroughly the rich dynamics of resistance switching memories, and designing circuits without a comprehensive picture of the nonlinear behaviour of these devices may lead to the realization of technical systems failing to operate as desired. Converting traditional circuits to memristive equivalents may require the adaptation of classical methods from nonlinear system theory. This paper extends the theory of time- and space-invariant standard cellular nonlinear networks with first-order processing elements for the case where a single non-volatile memristor is inserted in parallel to the capacitor in each cell. A novel nonlinear system-theoretic method allows to draw a comprehensive picture of the dynamical phenomena emerging in the memristive mem-computing array, beautifully illustrated in the so-called Primary Mosaic for the class of uncoupled memristor cellular nonlinear networks. Employing this new analysis tool it is possible to elucidate, with the support of illustrative examples, how to design variability-tolerant bio-inspired cellular nonlinear networks with second-order memristive cells for the execution of computing tasks or of memory operations. The capability of the class of memristor cellular nonlinear networks under focus to store and process information locally, without the need to insert additional memory units in each cell, may allow to increase considerably the spatial resolution of state-of-the-art purely CMOS sensor-processor arrays. This is of great appeal for edge computing applications, especially since the Internet-of-Things industry is currently calling for the realization of miniaturized, lightweight, low-power, and high-speed mem-computers with sensing capability on board.

The effect of localized strain on the electrical characteristics of curved carbon nanotubes

Carbon nanotubes (CNTs) are the emerging alternative for silicon for developing miniatured electromechanical devices in the More than Moore's era. But, the inconsistent pitch distances among the aligned CNTs have limited their outstanding performances. Except for the intertube overlapping, the curved morphology is an important but often ignored factor for the attractive CNTs under van der Waals interaction. Here, we have synthesized a clean and curved CNT structure with a definite curvature radius by introducing micro perturbation. Electrical measurement has demonstrated that the curved structure will limit the on/off ratio by orders of magnitude but can maintain a high output delivery in transistors. This is attributed to the resistance induced by the localized strain and the extra current delivery capability of the inner walls, which can be well explained by the energy band diagram model. Among the curved CNTs, incommensurate double walled CNTs of higher diameter difference are the optimal candidates for delivering a high current output by limiting intertube charge transfer. Our demonstrations and analysis have highlighted the importance of controlling both the chiral structures and morphology of CNTs for the applications of high-performance carbon-based electronics.

From active phased array antenna to antenna array microsystem in post-Moore era

In this review, we analyze and study the characteristics, current status, developing trend, and bottleneck technologies of active phased array antennas by highlighting the high-resolution earth observation microwave imaging radar demands for highly-efficient, low-profile, and lightweight antennas. We present the concept and contents of antenna array microsystem and several leading-edge technology issues based on predications of integrated circuits (ICs) development in the post Moore era. The multi-physics coupling model under the micro-nano scale involved in antenna array microsystem, critical technologies such as microwave semiconductor ICs, hybrid/heterogeneous integration, packaging and functional materials, and their solutions are described and explored. This study prospects the antenna array microsystem potentially applied in the next generation of microwave imaging radar.