Montgomery Multiplication Algorithm Research Articles

Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2

This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic architectures result in parallelized, DSP48E2-optimized scheduling of operations analogous to the FIOS block variant of the Montgomery Multiplication. We explore the impacts of different pipelining strategies within DSP blocks, scheduling of operations, processing element configurations, global design structures and their tradeoffs in terms of performance and resource costs. We discuss the application of our methodology to multiple types of DSP primitives. We provide ready-to-use fast, efficient, and fully parametrizable designs, which can adapt to a wide range of requirements and applications. Implementations are scalable to any operand width. Our most efficient designs can perform 128, 256, 512, 1024, 2048, and 4096 bits Montgomery modular multiplications in 0.0992 μs, 0.2032 μs, 0.3952 μs, 0.7792μs, 1.550 μs, and 3.099 μs using 4, 6, 11, 21, 41, and 82 DSP blocks, respectively.

Low-Complexity One-Dimensional Parallel Semi-Systolic Structure for Field Montgomery Multiplication Algorithm Perfect for Small IoT Edge Nodes

The use of IoT technology in several applications is hampered by security and privacy concerns with IoT edge nodes. Security flaws can only be resolved by implementing cryptographic protocols on these nodes. The resource constraints of the edge nodes make it extremely difficult to implement these protocols. The majority of cryptographic protocols’ fundamental operation is finite-field multiplication, and their performance is significantly impacted by their effective implementation. Therefore, this work mainly focuses on implementing low-area with low-energy and high-speed one-dimensional bit-parallel semi-systolic multiplier for the Montgomery multiplication algorithm. The space and delay complexity analysis of the proposed multiplier structure reveals that the proposed design has a significant reduction in delay and a marginal reduction in the area when compared to the competitive one-dimensional multipliers. The obtained ASIC synthesis report demonstrates that the suggested multiplier architecture saves a marginal amount of space as well as a significant amount of time, area–delay product (ADP), and power–delay product (PDP) when compared to the competitive ones. The obtained results indicate that the proposed multiplier layout is very appropriate for use in devices with limited resources such as IoT edge nodes and tiny embedded devices.

ПОРІВНЯЛЬНИЙ АНАЛІЗ ФУНКЦІЙ ОБЧИСЛЕННЯ МОДУЛЬНОЇ ЕКСПОНЕНТИ

The computation of the modular exponentiation for big numbers is widely used to find the discrete logarithm, in number-theoretic transforms and in cryptographic algorithms. To efficient compute the modular exponent, new methods, algorithms and means of their implementation are being developed. There are three directions of computational method of modular exponentiation: general modular exponentiation, and computation of the modular exponentiation with a fixed exponent or with a fixed base. Special functions have been developed to perform modular exponentiation in mathematical and cryptographic software libraries. The paper compares the freely available functions of computing the modular exponentiation from the Crypto ++, OpenSSL, Pari / GP and MPIR libraries and developed three functions based on the right-to-left binary shift algorithm. A separate type of numeric data from the MPIR library is used to work with big numbers in the developed functions. The developed functions implement a binary iterative algorithm in one main stream, in two streams and one stream using precomputation. The comparison is based on the average time of execution of the modular exponentiation for pseudo-random data with 1K and 2K bits, which corresponds to the size of about 300 and 600 decimal signs. The runtime results summarized in the table show that the modular exponentiation is computed the fastest by a function from the OpenSSL library, which is almost twice smaller than the function from the Crypto ++ library and three times smaller than the MPIR function in universal computer systems. The implementation of the function of computing the modular exponentiation by mathematical and cryptographic software libraries uses a more optimal modulus multiplication algorithm, the so-called Montgomery multiplication. The developed three functions use multiplication by modulo operations for factors smaller than the module value. The function using precomputation of the remainders for the fixed basis and the module is analyzed separately. After all, in the testing process, the time of precomputation and determination of the periodicity of residues for this function is not taken into account. Further parallelization of the computation of parts of a multi-bit exponent and the use of the Montgomery multiplication algorithm will allow efficient use of the developed function with precomputation for the calculation of the discrete logarithm.

Low latency Montgomery multiplier for cryptographic applications

In this modern era, data protection is very important. To achieve this, the data must be secured using either public-key or private-key cryptography (PKC). PKC eliminates the need of sharing key at the beginning of communication. PKC systems such as ECC and RSA is implemented for different security services such as key exchange between sender, receiver and key distribution between different network nodes and authentication protocols. PKC is based on computationally intensive finite field arithmetic operations. In the PKC schemes, modular multiplication (MM) is the most critical operation. Usually, this operation is performed by integer multiplication (IM) followed by a reduction modulo M. However, the reduction step involves a long division operation that is expensive in terms of area, time and resources. Montgomery multiplication algorithm facilitates faster MM operation without the division operation. In this paper, low latency hardware implementation of the Montgomery multiplier is proposed. Many interesting and novel optimization strategies are adopted in the proposed design. The proposed Montgomery multiplier is based on school-book multiplier, Karatsuba-Ofman algorithm and fast adders techniques. The Karatsuba-Ofman algorithm and school-book multiplier recommends cutting down the operands into smaller chunks while adders facilitate fast addition for large size operands. The proposed design is simulated, synthesized and implemented using Xilinx ISE Design Suite by targeting different Xilinx FPGA devices for different bit sizes (64-1024). The proposed design is evaluated on the basis of computational time, area consumption, and throughput. The implementation results show that the proposed design can easily outperform the state of the art

High-Performance FPGA Accelerator for SIKE

New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were over-estimated [#AdjCCMR18, #SIKESubmission2]. In this paper, we develop a highly optimized \mathbb{F}_{p} Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We furthermore improve the scheduling for our program Rom. As SIKE Stays as an alternate candidate in Round 3 of standardization it has high potential to be standardized in Round 4. Therefore, we implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Artix 7 and Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 38% faster and occupies 30% less hardware resources in comparison to the leading counterpart available in the literature [#brian-2019] and implementations for other security levels achieved similar improvement.

Implementation of VLSI Architecture for Montgomery Modular Multiplier

The paper proposes a Montgomery Modular Multiplier (MMM) using a simple and efficient Montgomery multiplication algorithm. Here a modification in the form of using hybrid full adders in the Carry Save adder is proposed. The hybrid full adder is designed using a conventional Complementary Metal Oxide Semiconductor and transmission gate logic. There is about 54% and 55% reduction of area (no. of components) in Radix 2 MMM and Semi-Carry-Save (SCS) based MMM with hybrid full adders. There is significant reduction in the power dissipation of 52% for Radix 2 MMM and 46% of SCS based MMM when hybrid adders are used instead of C-CMOS Full-Adders. The delay is also reduced by 47% in SCS based MMM as compared to that of Radix 2 MMM. The software used are Xilinx ISE 14.2 and Mentor Graphics Pyxis Schematic in 180-nm technology.

Area and Delay Efficient Compressor Based Montgomery Multiplier

Modular multiplication plays an important role in public-key crypto-systems. It first performs integer multiplication and then the costlier division operation is done. Due to this, the computation time and resource requirements will be high. In order to overcome these limitations, Montgomery Modular Multiplication (MMM) method is widely used. As integer multiplication is the most important operation in the Montgomery Multiplication algorithm, it becomes mandatory to enhance the speed of Integer Multiplier (IM) so that it can increase the overall efficiency of Montgomery Multiplier (MM). This work is mainly focused on compressor based MM to improve the performance in respect to propagation delay and area. In this paper, MM using 3:2, 4:2 and 5:2 compressors based Array Multiplier (AM) are designed for performing Integer Multiplication in MM and their performance are evaluated. The modules are synthesized using Xilinx ISE 14.7 and targeted on FPGA family Artix-7. Finally, comparative analysis is made in terms of delay and area

FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers

Systolic all-one-polynomial (AOP) multipliers usually suffer from the problem of high register complexity, especially in field-programmable gate array (FPGA) platforms where the register resources are not that abundant. In this paper, we have shown that the AOP-based systolic multipliers can easily achieve low register-complexity implementations and the proposed architectures can be employed as computation cores to derive efficient implementations of systolic Montgomery multipliers based on trinomials. First, we propose a novel data broadcasting scheme in which the register complexity involved within existing AOP-based systolic multipliers is significantly reduced. We have found out that the modified AOP-based structure can be packed as a standard computation core. Next, we propose a novel Montgomery multiplication algorithm that can fully employ the proposed AOP-based computation core. The proposed Montgomery algorithm employs a novel precomputed-modular operation, and the systolic structures based on this algorithm fully inherit the advantages brought from the AOP-based core (low register complexity, low critical-path delay, and low latency) except some marginal hardware overhead brought by a precomputation unit. The proposed architectures are then implemented by Xilinx ISE 14.1 and it is shown that compared with the existing designs, the proposed designs achieve at least 61.8% and 47.6% less area-delay product and power-delay product than the best of competing designs, respectively.

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry-save format to the binary representation, leading to a low hardware cost and short critical path delay at the expense of extra clock cycles for completing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), which could be one full-adder or two serial half-adders, is proposed to reduce the extra clock cycles for operand precomputation and format conversion by half. In addition, a mechanism that can detect and skip the unnecessary carry-save addition operations in the one-level CCSA architecture while maintaining the short critical path delay is developed. As a result, the extra clock cycles for operand precomputation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and significant area–time product improvement when compared with previous designs.

Montgomery Multiplier for Faster Cryptosystems

With the advancement in communication systems, security is a prime concern which is offered by cryptosystems Modular arithmetic is core operation in most of the cryptosystems. Many cryptosystems including RSA, DSA and ECC systems requires modular multiplication for private key generation. It uses modular exponentiation of large numbers to encrypt data, which is a slow process due to repeated modular multiplications. The efficiency of cryptography systems practically depend on how fast the modular multiplication is done, since these are at the base of computation. Many hardware and software implementations for faster modular multiplication have been proposed, Montgomery Multiplication Algorithm is recognized as the most efficient among these. This paper presents a 32-bit implementation of a Faster Montgomery algorithm for performing modular multiplication. The algorithm is based on the method proposed by Montgomery for modular multiplication and is complementary to the available techniques. Simulation shows that our design performs faster in terms of clock frequency while it requires lower area.

A semi-systolic Montgomery multiplier over <i>GF</i>(2<i><sup>m</sup></i>)

In this study, we present an efficient finite field arithmetic architecture based on systolic array for multiplication which is a core algorithm for division and exponentiation operations. In order to obtain dedicated area-efficient circuits, we adopt Montgomery multiplication algorithm and systolic array. First of all we induce an efficient arithmetic algorithm from typical Montgomery multiplication using an effective factor, then we design an efficient semi-systolic array based multiplication architecture which is highly suitable for pipelined operations. The proposed multiplier saves at least 40% area complexity as compared to the corresponding existing structures.

Multifunction Residue Architectures for Cryptography

A design methodology for incorporating Residue Number System (RNS) and Polynomial Residue Number System (PRNS) in Montgomery modular multiplication in GF(p) or GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) respectively, as well as a VLSI architecture of a dual-field residue arithmetic Montgomery multiplier are presented in this paper. An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters and between the two residue representations. A versatile architecture is derived that supports all operations of Montgomery multiplication in GF(p) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ), input/output conversions, Mixed Radix Conversion (MRC) for integers and polynomials, dual-field modular exponentiation and inversion in the same hardware. Detailed comparisons with state-of-the-art implementations prove the potential of residue arithmetic exploitation in dual-field modular multiplication.

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

Montgomery multiplication is the kernel operation in public key ciphers. Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors. Several multicore platforms are designed to verify the efficiency of parallelization. The fastest platform takes 3460 cycles to finish a 1024-b Montgomery multiplication, which is six times faster than a single MIPS processor and three times faster than the pSHS parallelization based on a platform with eight MicroBlaze cores.

유한 체상의 몽고메리 알고리즘 및 하드웨어 구조 설계

유한체상의 곱셈기는 오류 제어 코드, 암호시스템 및 디지털 신호처리와 같은 여러 분야의 기본적인 구성 요소이다. 최근 다양한 유한체상의 곱셈기가 세미-시스톨릭 구조를 기반으로 제안되었다. 또한, 몽고메리 알고리즘은 효율적인 곱셈 연산 알고리즘으로 잘 알려져 있다. 본 논문은 유한체 상에서 다항식 표현을 사용하여 효율적인 몽고메리 곱셈 알고리즘을 유도하고 이를 기반으로 세미-시스톨릭 몽고메리 곱셈기를 제안한다. 제안한 곱셈기는 병렬 구조에 적합한 몽고메리 인자를 선택하였으며 전체 계산 구조를 두 부분으로 나누어 동시에 계산할 수 있다. 제안한 곱셈기는 기존의 곱셈기에 비해 시간 복잡도를 30%~50% 정도 줄임으로써 전체 시간 복잡도의 30% 정도를 줄였다. Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Recently, many semi-systolic architectures have been proposed for multiplications over finite fields. Also, Montgomery multiplication algorithm is well known as an efficient arithmetic algorithm. In this paper, we induce an efficient multiplication algorithm and propose an efficient semi-systolic Montgomery multiplier based on polynomial basis. We select an ideal Montgomery factor which is suitable for parallel computation, so our architecture is divided into two parts which can be computed simultaneously. In analysis, our architecture reduces 30%~50% of time complexity compared to typical architectures.

The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption

One of the key points of success in high performance computation using an FPGA is the efficient usage of DSP slices and block RAMs in it. This paper presents a FDFM (Few DSP slices and Few block RAMs) processor core approach for implementing RSA encryption. In our approach, an efficient hardware algorithm for Chinese Remainder Theorem (CRT) based RSA decryption using Montgomery multiplication algorithm is implemented. Our hardware algorithm supporting up-to 2048-bit RSA decryption is designed to be implemented using one DSP slice, one block RAM and few logic blocks in the Xilinx Virtex-6 FPGA. The implementation results show that our RSA core for 1024-bit RSA decryption runs in 13.74ms. Quite surprisingly, the multiplier in the DSP slice used to compute Montgomery multiplication works in more than 95% clock cycles during the processing. Hence, our implementation is close to optimal in the sense that it has only less than 5% overhead in multiplication and no further improvement is possible as long as CRT-based Montgomery multiplication based algorithm is applied. We have also succeeded in implementing 320 RSA decryption cores in one Xilinx Virtex-6 FPGA XC6VLX240T-1 which work in parallel. The implemented parallel 320 RSA cores achieve 23.03 Mbits/s throughput for 1024-bit RSA decryption.

New Hardware Architectures for Montgomery Modular Multiplication Algorithm

Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc proposed the Multiple-Word Radix-2 Montgomery Multiplication (MWR2MM) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper, we propose two new hardware architectures that are able to perform the same operation in approximately n clock cycles with almost the same clock period. These two architectures are based on precomputing partial results using two possible assumptions regarding the most significant bit of the previous word. These two architectures outperform the original architecture of Tenca and Koc in terms of the product latency times area by 23 and 50 percent, respectively, for several most common operand sizes used in cryptography. The architecture in radix-2 can be extended to the case of radix-4, while preserving a factor of two speedup over the corresponding radix-4 design by Tenca, Todorov, and Koc from CHES 2001. Our optimization has been verified by modeling it using Verilog-HDL, implementing it on Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm

This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation

This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first one is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in an FPGA. The second one is to balance and improve the circuit delay. The third one is to ensure scalability of the circuit. Our architecture can perform fast operations using small-scale resources; in particular, it can complete a 512-bit modular exponentiation as fast as in 0.26ms with the smallest Virtex-4 FPGA, XC4VF12-10SF363. In fact the number of SLICEs used is approx. 4200, which proves the compactness of our design. Moreover, the scalability of our design also allows 1024-, 1536-, and 2048-bit modular exponentiations to be processed in the same circuit.

Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of ${\rm GF}(2^{m})$

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ?m/L?, m is the word size and L is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems

This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix-vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 × 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2n) at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.