Montgomery Multiplication Research Articles

High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion

Modular multiplication is a key operation in RSA cryptosystems. Modular multipliers can be realized using Montgomery algorithm. Montgomery algorithm employing carry save adders makes modular multiplication suitable and efficient. Montgomery modular multiplication can be carried out in two ways. All the operands are kept in carry save form in one of the ways. The input and output are kept in binary form, and intermediate operands are kept in carry save form in the other way which requires an efficient format converter. This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method. Format conversion is carried out through a format conversion unit which consists of a carry look-ahead unit and multiplexer unit. In addition, this multiplier merges two iterations, which reduces the number of clock cycles significantly. Merger of iteration requires integer multiples of inputs which is computed using the same format converter. Critical path delay of the multiplier is minimized by multiplying one of the inputs by four which simplifies necessary intermediate calculations. The total time required for one complete multiplication is significantly minimized due to reduction in required number of clock cycles with optimum critical path delay. Experimental results show that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial ${P(x)}$ , which affects final hardware implementation. This paper presents a computer algebra technique that performs verification and reverse engineering of GF( ${2^{m}}$ ) multipliers directly from the gate-level implementation. The approach is based on extracting a unique irreducible polynomial in a parallel fashion and proceeds in three steps: 1) determine the bit position of the output bits; 2) determine the bit position of the input bits; and 3) extract the irreducible polynomial used in the design. We demonstrate that this method is able to reverse engineer GF( ${2^{m}}$ ) multipliers in ${m}$ threads. Experiments performed on synthesized Mastrovito and Montgomery multipliers with different ${P(x)}$ , including NIST-recommended polynomials, demonstrate high efficiency of the proposed method.

DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDER

Ponte Academic JournalNov 2019, Volume 75, Issue 11 DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDERAuthor(s): P. Manju ,T. MadhaviJ. Ponte - Nov 2019 - Volume 75 - Issue 11 doi: 10.21506/j.ponte.2019.11.7 Abstract:In cryptographic applications modular multiplications are most widely used. This modular multiplication depends on the addition and shifting operations. While performing iteration operation in modular multiplication, right shift operation with complete word architecture is performed. In the same way arithmetic unit is used in the multiplier to perform the arithmetic operations. While designing arithmetic unit, optimized multipliers are used most widely. Here a high speed hybrid multiplier using hybrid transistor logic adder is presented in this paper. This advanced Montgomery modular multiplication is based on the modular exponentiations to obtain high speed. The Montgomery multiplication uses adequate hardware implementation. The hybrid transistor logic multiplier system not only depends on the modular exponentiations but also depends on the modular multiplication to reduce the delay. Hence compared to Hybrid transistor logic adder system, the hybrid transistor logic multiplier system gives effective results in terms of speed, area and delay. Download full text:Check if you have access through your login credentials or your institution Username Password

Performance Improvement of Montgomery Multiplier Architecture Using Pre-Computation and Unfolding Technique

Performance Improvement of Montgomery Multiplier Architecture Using Pre-Computation and Unfolding Technique

Collaboration of Trusted Node and QoS Based Energy Multi Path Routing Protocol for Vehicular Ad Hoc Networks

In the recent past information transmission through the vehicular ad hoc network (VANET) playing a vital role due to increase in accident statistics. There are numerous networking and VANET protocols helpful to control the trust while transmitting the data from source to destination nodes in traffic environment. In spite of many existing protocols for analyzing the trust in the network, the challenge of routing overhead, high energy consumption and malicious attacks issues still continue in the communication. This research introduces the trust collaboration nodes and Quality of Service (QoS) with energy multipath routing protocol for transmitting the information through VANET. Initially, the trusted nodes have been collected for analyzing the neighbouring nodes and the information are transmitted using the proposed QoS based energy efficient multipath routing protocol. During this transmission, the multi path protocol eliminates the intermediate attacks effectively when compared with the other existing protocols. The Proposed protocol maintains the QoS while routing the information from source to destination and further the efficiency has been analyzed through simulation experiments and Montgomery multiplier based Elliptic Curve Cryptography (ECC) will be used in future for better security and privacy.

A Secure Algorithm for Inversion Modulo 2k

Modular inversions are widely employed in public key crypto-systems, and it is known that they imply a bottleneck due to the expensive computation. Recently, a new algorithm for inversions modulo p k was proposed, which may speed up the calculation of a modulus dependent quantity used in the Montgomery multiplication. The original algorithm lacks security countermeasures; thus, a straightforward implementation may expose the input. This is an issue if that input is a secret. In the RSA-CRT signature using Montgomery multiplication, the moduli are secrets (primes p and q). Therefore, the moduli dependent quantities related to p and q must be securely computed. This paper presents a security analysis of the novel method considering that it might be used to compute secrets. We demonstrate that a Side Channel Analysis leads to disclose the data being manipulated. In consequence, a secure variant for inversions modulo 2 k is proposed, through the application of two known countermeasures. In terms of performance, the secure variant is still comparable with the original one.

RNS Montgomery reduction algorithms using quadratic residuosity

The residue number system (RNS) is a method for representing an integer as an n-tuple of its residues with respect to a given base. Since RNS has inherent parallelism, it is actively researched to implement a faster processing system for public-key cryptography. This paper proposes new RNS Montgomery reduction algorithms, Q-RNSs, the main part of which is twice a matrix multiplication. Letting n be the size of a base set, the number of unit modular multiplications in the proposed algorithms is evaluated as (2n^2+n). This is achieved by posing a new restriction on the RNS base, namely, that its elements should have a certain quadratic residuosity. This makes it possible to remove some multiplication steps from conventional algorithms, and thus the new algorithms are simpler and have higher regularity compared with conventional ones. From our experiments, it is confirmed that there are sufficient candidates for RNS bases meeting the quadratic residuosity requirements.

SIDH on ARM: Faster Modular Multiplications for Faster Post-Quantum Supersingular Isogeny Key Exchange

We present high-speed implementations of the post-quantum supersingular isogeny Diffie-Hellman key exchange (SIDH) and the supersingular isogeny key encapsulation (SIKE) protocols for 32-bit ARMv7-A processors with NEON support. The high performance of our implementations is mainly due to carefully optimized multiprecision and modular arithmetic that finely integrates both ARM and NEON instructions in order to reduce the number of pipeline stalls and memory accesses, and a new Montgomery reduction technique that combines the use of the UMAAL instruction with a variant of the hybrid-scanning approach. In addition, we present efficient implementations of SIDH and SIKE for 64-bit ARMv8-A processors, based on a high-speed Montgomery multiplication that leverages the power of 64-bit instructions. Our experimental results consolidate the practicality of supersingular isogeny-based protocols for many real-world applications. For example, a full key-exchange execution of SIDHp503 is performed in about 176 million cycles on an ARM Cortex-A15 from the ARMv7-A family (i.e., 88 milliseconds @2.0GHz). On an ARM Cortex-A72 from the ARMv8-A family, the same operation can be carried out in about 90 million cycles (i.e., 45 milliseconds @1.992GHz). All our software is protected against timing and cache attacks. The techniques for modular multiplication presented in this work have broad applications to other cryptographic schemes.

A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor

The existing Power Analysis Attacks (PAA) resilient adiabatic logic designs exhibit variations in current peaks, have asymmetric structures and suffer from Non-Adiabatic Losses (NAL) during the evaluation phase of the power-clock. However, asymmetric structure and variations in current peaks make the circuit susceptible to PAA. In this paper, we present a novel PAA resilient adiabatic logic which has a symmetric structure, completely removes NAL from the evaluation phase of the power-clock and exhibits minimal variations in current peaks for gates as well as in an 8-bit Montgomery multiplier. The proposed logic has been compared with three existing secure adiabatic logic designs for operating frequencies ranging from 1 MHz to 100 MHz and power-clock scaling ranging from 1.8 V to 0.6 V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) at the frequencies mentioned above. In addition, all the 2-input gates using proposed logic dissipate average energy within 0.3% of each other and thus, lowest value of standard deviation at all the simulated frequencies. The simulation results for the 8-bit Montgomery multiplier show that proposed logic exhibits the least value of NED and NSD at all the simulated frequencies and under power-supply scaling.

High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications

Modular multiplication is the most crucial operation in many public-key crypto-systems, which can be accomplished by integer multiplication followed by a reduction scheme. The reduction scheme involves a division operation that is costly in terms of computation time and resource consumption both on hardware and software platforms. Montgomery modular multiplication is widely used to eliminate the costly division operation. This work presents an efficient implementation of full-word Montgomery modular multiplication. This incorporates the more efficient Karatsuba algorithm where the complexity of multiplication is reduced form O(n2) to O(n1.58). The Karatsuba algorithm recommends to split the operands into smaller chunks. Two methods of operand splitting are exploited: (1) Four Parts (FP) splitting and (2) Deep Four Parts (DFP) splitting. These methods are then used in the design of Integer Multiplier (IM) and Montgomery Multiplier (MM). The design is synthesized using Xilinx ISE 14.1 Design Suite for Virtex-5, Virtex-6 and Virtex-7. Compared with the traditional implementations, the proposed scheme outperforms all other designs in terms of throughput and area-delay product. Moreover, the proposed scheme utilizes the least hardware resources in the known literature. The proposed MM design is able to compute modular multiplication for the Elliptic Curve Cryptography (ECC) field sizes of 192–512 bits.

A fast digit based Montgomery multiplier designed for FPGAs with DSP resources

A fast Montgomery multiplier design utilizing the DSP resources in modern FPGAs is presented. In the proposed design, the operand size is the multiples of 528 bits and the digit size is 48 bits. The design has 48 × 48 bit digit multipliers built from the DSP slices performing 24 × 16 bit multiplications and a carry select accumulator built from the DSP slices performing 48 bit additions. The proposed Montgomery multiplier works iteratively. In each iteration, a digit of an operand is multiplied by the digits of the other, the result is accumulated, and reduced by Montgomery method. An iteration takes not one but eight cycles to keep the digit multiplier count low and save some hardware resources. The proposed design is implemented for Virtex-7 FPGAs. The performance results are comparable with the best results in the literature. Substantial savings in FPGA logic resources are obtained.

A Vendor-Neutral Unified Core for Cryptographic Operations in GF(p) and GF(2m) Based on Montgomery Arithmetic

In the emerging IoT ecosystem in which the internetworking will reach a totally new dimension the crucial role of efficient security solutions for embedded devices will be without controversy. Typically IoT-enabled devices are equipped with integrated circuits, such as ASICs or FPGAs to achieve highly specific tasks. Such devices must have cryptographic layers implemented and must be able to access cryptographic functions for encrypting/decrypting and signing/verifying data using various algorithms and generate true random numbers, random primes, and cryptographic keys. In the context of a limited amount of resources that typical IoT devices will exhibit, due to energy efficiency requirements, efficient hardware structures in terms of time, area, and power consumption must be deployed. In this paper, we describe a scalable word-based multivendor-capable cryptographic core, being able to perform arithmetic operations in prime and binary extension finite fields based on Montgomery Arithmetic. The functional range comprises the calculation of modular additions and subtractions, the determination of the Montgomery Parameters, and the execution of Montgomery Multiplications and Montgomery Exponentiations. A prototype implementation of the adaptable arithmetic core is detailed. Furthermore, the decomposition of cryptographic algorithms to be used together with the proposed core is stated and a performance analysis is given.

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

Fast and High-throughput Montgomery Modular Multiplier for RSA Encryption and Decryption

This paper proposes a fast and high-throughput Montgomery modular multiplier that outputs a modular product in binary form. Intermediate operands are kept in carry-save form and added through a two-level, carry-save adder architecture. A carry look-ahead adder is also employed in this multiplier for operand pre-computation and converting the final output from carrysave form to binary form, which accounts for additional clock cycles. The proposed multiplier computes the next two quotients during the iSUPth/SUP iteration to minimize critical path delay, and computes intermediate output for the (i + 2)SUPth/SUP iteration while skipping the (і + 1)SUPth/SUP iteration. In this way, the overall time required for multiplication is minimized significantly, and additional clock cycles required for operand pre-computation and format conversion can be ignored. Experimental results show that the proposed Montgomery modular multiplier can achieve significant speed and throughput improvement, compared to previous designs.

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations

Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present “Without Charge-Sharing Quasi-Adiabatic Logic”, WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz.

Computation of the 100 quadrillionth hexadecimal digit of π on a cluster of Intel Xeon Phi processors

Abstract This paper presents the computation of a specific hexadecimal digit of π by using a Bailey–Borwein–Plouffe (BBP)-type formula on a cluster of Intel Xeon Phi processors. The BBP-type formula can be computed using modular exponentiation. We use Montgomery multiplication for the modular multiplication, which is the most time-consuming part of the modular exponentiation. We vectorize multiple modular exponentiations and multiple integer divisions by using Intel Advanced Vector Extensions 512 (Intel AVX-512) instructions. A parallel implementation of the BBP-type formula is presented. The 100 quadrillionth hexadecimal digit of π was computed on a 512-node cluster of Intel Xeon Phi processors with an elapsed time of 641 h 29 min that includes the time required for verification.

Accelerating Digital Forensics through Parallel Computing

Digital crimes in the era of big data and cloud computing imposes significant challenges in digital forensics. Cloud environment provides low cost, easy management and reasonable solutions. Moreover, it supports big data structures and solutions (i.e., security, privacy and digital forensics). In order to achieve a secure digital forensics analysis in cloud environment, researchers have proposed solutions with expensive communication cost and computation overheads. Among these solutions Nasereldin et al. proposed a protocol which solves the problem of authenticity and integrity of evidence using signcryption technique. This leads to low communication and implementation overheads. Furthermore, identity-based cryptography is used to solve Public Key Infrastructure (PKI) problems. In addition, it is characterized by the ability to divide the message into small messages which is suitable for pipelining techniques. Nasreldin et al.'s signcryption protocol is based on Elliptic Curve Cryptography (ECC) which is implemented by using different mathematical operations. In this protocol, ECC mathematical operations take huge time during the execution of the algorithm. ECC consists of point doubling and point addition operations. These operations require the execution of many Montgomery modular multiplications that consume time. In this study, we introduce a technique to speed up ECC operations in order to enhance the efficiency of Nasreldin et al. protocol. In particular, we propose a multi-stage parallel design which consists of three stages. First, we speed up the point doubling and point addition operation. Secondly, we enhance the execution time of Montgomery multiplications. Finally, pipelining is used to obtain a better performance. The results show that the proposed design enhances Nasreldin et al. protocol’s execution time by 47.1, 64.7, 73.5 and 79.4%, assuming that the number of nodes is 2, 4, 6 and 12, respectively.

VLSI Implementation of High Performance Montgomery Modular Multiplication

VLSI Implementation of High Performance Montgomery Modular Multiplication

FFT-based McLaughlin's Montgomery Exponentiation without Conditional Selections

Modular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively.

Secure and compact implementation of optimized Montgomery multiplier based elliptic curve cryptography on FPGA with road vehicular traffic collecting protocol for VANET application

Secure and compact implementation of optimized Montgomery multiplier based elliptic curve cryptography on FPGA with road vehicular traffic collecting protocol for VANET application