Circuit Complexity Research Articles

Integrated Bionic Human Retina Process and In‐Sensor RC System Based on 2D Retinomorphic Memristor Array

AbstractThe rapid development of machine vision has put forward higher requirements for image perception and visual learning systems. However, limited by the von Neumann bottleneck, traditional artificial vision systems rely on complex optical and circuit designs, and the separate distribution of sensors, memory, and computing modules results in high energy consumption and high latency. Memristor‐based reservoir computing (RC) system with integrated sensing and memory functions provides a solution to effectively improve the computational efficiency of artificial vision networks. Here, a complete artificial visual recognition system based on in‐sensor RC is developed by combining the excellent optoelectronic synaptic properties of 2D WS2 memristor array. Through effectively regulating the conductance of memristors by light or electrical stimulation, image information is converted into high‐dimensional information in the reservoir layer, and the classification can be completed by simple training, significantly reducing the training complexity and cost consumption. With this system, an effective recognition of hand‐written numbers with an accuracy of 88.3% is demonstrated, and a 100% recognition of traffic signals of different colors is achieved. The proposed in‐sensor RC system advances the development and application of artificial vision recognition, paving the way for efficient machine learning and neuromorphic vision systems.

Q-Map: quantum circuit implementation of boolean functions

Quantum computing has gained attention in recent years due to the significant progress in quantum computing technology. Today many companies like IBM, Google and Microsoft have developed quantum computers and simulators for research and commercial use. The development of quantum techniques and algorithms is essential to exploit the full power of quantum computers. In this paper we propose a simple visual technique (we call Q-Map) for quantum realization of classical Boolean logic circuits. The proposed method utilizes concepts from Boolean algebra to produce a quantum circuit with minimal number of quantum gates.

Cell cycle-driven transcriptome maturation confers multilineage competence to cardiopharyngeal progenitors.

During development, stem and progenitor cells divide and transition through germ layer- and lineage-specific multipotent states to generate the diverse cell types that compose an animal. Defined changes in biomolecular composition underlie the progressive loss of potency and acquisition of lineage-specific characteristics. For example, multipotent cardiopharyngeal progenitors display multilineage transcriptional priming, whereby both the cardiac and pharyngeal muscle programs are partially active and coexist in the same progenitor cells, while their daughter cells engage in a cardiac or pharyngeal muscle differentiation path only after cell division. Here, using the tunicate Ciona, we studied the acquisition of multilineage competence and the coupling between fate decisions and cell cycle progression. We showed that multipotent cardiopharyngeal progenitors acquire the competence to produce distinct Tbx1/10(+) and (-) daughter cells shortly before mitosis, which is necessary for Tbx1/10 activation. By combining transgene-based sample barcoding with single cell RNA-seq (scRNA-seq), we uncovered transcriptome-wide dynamics in migrating cardiopharyngeal progenitors as cells progress through G1, S and G2 phases. We termed this process "transcriptome maturation", and identified candidate "mature genes", including the Rho GAP-coding gene Depdc1, which peak in late G2. Functional assays indicated that transcriptome maturation fosters cardiopharyngeal competence, in part through multilineage priming and proper oriented and asymmetric division that influences subsequent fate decisions, illustrating the concept of "behavioral competence". Both classic feedforward circuits and coupling with cell cycle progression drive transcriptome maturation, uncovering distinct levels of coupling between cell cycle progression and fateful molecular transitions. We propose that coupling competence and fate decision with the G2 and G1 phases, respectively, ensures the timely deployment of lineage-specific programs.

Performance evaluation of an automatic resonant switched capacitor-based voltage balancing circuits for series connected batteries

Electrical energy storage (EES) plays a crucial role in various power applications. Voltage imbalance is a common issue that can negatively affect the efficiency, reliability, and safety of EESs. Several types of voltage balancing (VB) circuits have been proposed in much of the literature. Among these VB circuits, switched capacitor (SC)-based circuits have attracted significant interest due to their efficiency, cost-effectiveness, compact size, and ease of control, but their balancing performance is not yet satisfactory. As a result, structural modifications in SC-based circuits have been widely proposed to improve balancing performance. However, not all of these circuit structures have been implemented into a resonant switched capacitor (RSC)-based voltage balancing, which has higher efficiency. Hence, this study aims to assess the efficiency of RSC-based VB circuits by conducting analog simulation using the Matlab Simulink software. This research evaluates the performance of the VB circuit not only in terms of its speed and efficiency, but also in terms of its energy distribution. The results show that the delta structure is the fastest in terms of balancing speed when completing the balancing process, followed by the mesh structure and the parallel structure. The best energy distribution is produced by a parallel structure, as indicated by the change in voltage of all battery cells always moving towards a convergent value, regardless of the variations in initial imbalance conditions. Meanwhile, other circuit structures distribute energy randomly, allowing the voltage of the battery cells to change not directly towards a convergent value. Lastly, the paper summarizes the balancing speed, efficiency, circuit complexity, and quality of energy distribution.

Selective metallization of polymer based on nanoscale tungsten oxide laser activators for advanced electronics

In recent years, laser-induced selective metallization (LISM) has been widely used to fabricate complex metal patterns and circuits due to its superior precision. Laser sensitizers known as laser-activated for electroless copper plating (ECP) are a significant premise in LISM. Herein, we confirmed that tungsten oxides (WO2.72, WO2.92, and WO3) exhibited excellent LISM activity due to oxygen vacancies (OVs) in their lattice. Moreover, non-stoichiometric tungsten (WO2.72, WO2.92) presented higher activity due to a higher concentration of OVs than the stoichiometric form of WO3, indicating the importance of OVs to the activity of laser sensitizers in LISM. Moreover, a higher OVs concentration in the laser sensitizer resulted in a higher LISM activity. This finding points out the direction for future laser sensitizer screening, synthesis, and development. After 30 min ECP, the square resistance of the prepared copper layer on ABS/WO2.72, ABS/WO2.92, and ABS/WO3 are 0.014, 0.035, and 0.176 Ω/sq, respectively. The nanoscale tungsten oxides with excellent LISM activity enabled the rapid fabrication of metal patterns and circuits in various scenarios, which expands the research field and application prospect of LISM technology. We demonstrate the advantages of LISM with tungsten oxides in fabricating advanced electronics. A strategy for replacing hand-wound windings in electromagnetic generators with 2D on-chip planar inductor arrays from LISM was proposed. The generated current reached a high level of 193 mA, and can be directly connected to wireless sensor networks to supply power. This work is the first research ever reporting laser sensitizers of tungsten oxides and introducing LISM technology into self-powered electronics.

Investigating Dynamic Behavior in SAG Mill Pebble Recycling Circuits: A Simulation Approach

The dynamics of milling circuits, particularly those involving Semi-Autogenous Grinding (SAG) mills, are not adequately studied, despite their critical importance in mineral processing. This paper aims to investigate the dynamic behavior of an SAG mill pebble recycling circuit under varying feed ore conditions, focusing on both uncontrollable parameters (such as ore hardness) and controllable parameters (including circuit layout and pebble crusher configurations). The study is carried out with Simulink dynamic simulations. Our findings reveal several key insights. Firstly, plant designs based solely on static simulations may not be adequate for large or complex circuits, as they fail to account for the dynamic nature of milling processes. Second, incorporating stockpiles after pebble crushing can effectively mitigate the impact of dynamic fluctuations, leading to more stable circuit performance. Third, different circuit layouts can facilitate easier maintenance and operational flexibility. Notably, finer pebble crushing can enhance circuit throughput by 5% to 10%.

A novel design of multiplexer based on the cellular interaction in quantum dot technology with energy dissipation analysis

This paper addresses the challenge of efficiently designing multiplexer structures in quantum-dot technology circuits. Specifically, it introduces a novel approach to constructing a 2-to-1 multiplexer through a unique gate design that relies on the interaction between cells. The key focus of this design is to minimize the utilization of cells, thereby conserving space and facilitating the creation of more complex combinational and sequential circuits. The methodology involves developing a gate structure that requires the least number of cells compared to existing designs. This reduction in cell usage not only optimizes space utilization but also enhances the scalability of the multiplexer for integration into larger circuits. The proposed gate structure demonstrates a significant improvement, achieving a 15% reduction in the number of cells compared to the previously best-known design. To further evaluate the effectiveness of this novel gate design, the study extends its analysis to include the implementation of various complex circuits such as a 4-to-1 multiplexer, D latch, and T latch. These structures are synthesized using the newly proposed gate design as a fundamental building block. To validate the functionality and performance of these circuits, simulations are conducted using the QCADesigner simulation tool. This comprehensive simulation enables a thorough assessment of the proposed structures across different circuit configurations, providing insights into their operational efficiency and suitability for practical applications in quantum-dot technology.

A fully integrated charge pump with double-loop control and differentiator-based transient enhancer for neural stimulation applications

This paper proposes a fully integrated charge pump (CP) with a double-loop control and a differentiator-based transient enhancer (DTE) for high-voltage neural stimulation applications. The double-loop control includes a clock-supply-voltage (VCLK) modulation loop and a pulse-frequency modulation (PFM) loop. The VCLK modulation loop regulates the output voltage by adjusting VCLK while the PFM loop adjusts the operating frequency of the CP in accordance with the load current in order to improve power efficiency. The proposed CP combines the function of output voltage regulation and VCLK generation into a single unit, leading to significantly reduced circuit complexity. The proposed double-loop control is capable of dealing with different dc current requirements while the proposed DTE suppresses the undershoots and overshoots of the output voltage during load transients. The proposed CP has been simulated using a 0.18-μm triple-well CMOS process and occupies an area of 0.537 mm2. The post-layout simulation results show that it can provide a regulated 9-V output voltage from a 3.6-V input voltage with a peak power efficiency of 73.4 % at 2-mA load condition. The Monte-Carlo simulation demonstrates that the overshoot and undershoot of the output voltage are kept below 3 % when undergoing a 2-mA load transient.

Dynamic Cooling on Contemporary Quantum Computers

We study the problem of dynamic cooling whereby a target qubit is cooled at the expense of heating up N−1 further identical qubits by means of a global unitary operation. A standard back-of-the-envelope high-temperature estimate establishes that the target qubit temperature can be dynamically cooled by at most a factor of 1/N. Here we provide the exact expression for the minimum temperature to which the target qubit can be cooled and reveal that there is a crossover from the high initial temperature regime, where the scaling is 1/N, to a low initial temperature regime, where a much faster scaling of 1/N occurs. This slow, 1/N scaling, which was relevant for early high-temperature NMR quantum computers, is the reason dynamic cooling was dismissed as ineffectual around 20 years ago; the fact that current low-temperature quantum computers fall in the fast, 1/N scaling regime, reinstates the appeal of dynamic cooling today. We further show that the associated work cost of cooling is exponentially more advantageous in the low-temperature regime. We discuss the implementation of dynamic cooling in terms of quantum circuits and examine the effects of hardware noise. We successfully demonstrate dynamic cooling in a three-qubit system on a real quantum processor. Since the circuit size grows quickly with N, scaling dynamic cooling to larger systems on noisy devices poses a challenge. We therefore propose a suboptimal cooling algorithm, whereby relinquishing a small amount of cooling capability results in a drastically reduced circuit complexity, greatly facilitating the implementation of dynamic cooling on near-future quantum computers. Published by the American Physical Society 2024

Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods

Analog circuits composed by large number of nodes in a tightly coupled structure pose significant challenges due to their prohibitive CPU simulation time. This work describes a method to speed up the simulation of such circuits by means of the combination of space state formulation of circuit equations with explicit integration methods parallelized over a many-core processor such as a GPU. Although stability of explicit techniques require smaller integration steps compared to implicit methods, the proposed method employs a fast estimate of the maximum allowed step size to guarantee numerical stability, which yields a shorter simulation time for increasing complexity circuit architectures. Moreover, the proposed technique can be straightforward parallelized on a many core architecture. The proposed method is demonstrated with two examples using constant and variable coefficients respectively: an RLC interconnect and a MOS-C network to perform Gaussian filtering of medium resolution images. The results obtained have been compared to a parallel version of SPICE and show improvements up to two orders of magnitude for transient simulations depending of the circuit size.

Purely Optical, Reversible, Read‐Write‐Erase Cycling Using Photoswitchable Beads in Micropatterned Arrays

AbstractUsing surface‐templated electrophoretic deposition, arrays of polymer beads (photonic units) incorporating photo‐switchable DAE molecules are created, which can be reversibly and individually switched between high and low emission states by direct photo‐excitation, without any energy or electron transfer processes within the molecular system. The micropatterned array of these photonic units is spectroscopically characterized in detail and optimized with respect to both signal contrast and cross‐talk. The optimum optical parameters including laser intensity, wavelength and duration of irradiation are elucidated and ideal conditions for creating reversible on/off cycles in a micropatterned array are determined. 500 such cycles are demonstrated with no obvious on/off contrast attenuation. The ability to process binary information is demonstrated by selectively writing information to the given photonic unit, reading the resultant emissive signal pattern and finally erasing the information again, which in turn demonstrates the possibility of continuous recording. This basic study paves the way for building complex circuits using spatially well‐arranged photonic units.

Investigating Retinal Circuits and Molecular Localization by Pre-Embedding Immunoelectron Microscopy.

The retina comprises numerous cells forming diverse neuronal circuits, which constitute the first stage of the visual pathway. Each circuit is characterized by unique features and distinct neurotransmitters, determining its role and functional significance. Given the intricate cell types within its structure, the complexity of neuronal circuits in the retina poses challenges for exploration. To better investigate retinal circuits and cross-talk, such as the link between cone and rod pathways, and precise molecular localization (neurotransmitters or neuropeptides), such as the presence of substance P-like immunoreactivity in the mouse retina, we employed a pre-embedding immunoelectron microscopy (immuno-EM) method to explore synaptic connections and organization. This approach enables us to pinpoint specific intercellular synaptic connections and precise molecular localization and could play a guiding role in exploring its function. This article describes the protocol, reagents used, and detailed steps, including (1) retina fixation preparation, (2) pre-embedding immunostaining, and (3) post-fixation and embedding.

Quanto: optimizing quantum circuits with automatic generation of circuit identities

Existing quantum compilers focus on mapping a logical quantum circuit to a quantum device and its native quantum gates. Only simple circuit identities are used to optimize the quantum circuit during the compilation process. This approach misses more complex circuit identities, which could be used to optimize the quantum circuit further. We propose Quanto, the first quantum optimizer that automatically generates circuit identities. Quanto takes as input a gate set and generates provably correct circuit identities for the gate set. Quanto’s automatic generation of circuit identities includes single-qubit and two-qubit gates, which leads to a new database of circuit identities, some of which are novel to the best of our knowledge. In addition to the generation of new circuit identities, Quanto’s optimizer applies such circuit identities to quantum circuits and finds optimized quantum circuits that have not been discovered by other quantum compilers, including IBM Qiskit and Cambridge Quantum Computing Tket. Quanto’s database of circuit identities could be applied to improve existing quantum compilers and Quanto can be used to generate identity databases for new gate sets.

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation

ABSTRACT This article describes floating and grounded memristor emulator built with an Inverting Current Conveyor Transconductance Amplifier (ICCTA). One ICCTA, one capacitor, and three resistors are used to implement the charge controlled floating memristor emulator. In contrast, a flux controlled grounded memristor emulator consists of one ICCTA, one resistor, and one capacitor. Both presented circuits do not incorporate complex circuits such as analog multiplier circuits, passive inductors, and analog to digital converter circuits in their implementation, which is advantageous in terms of circuit realisation. The designed circuits may be operated in incremental as well as decremental configurations by appropriate setting of MOS switches. In addition, PVT (process, voltage, and temperature) analysis of the proposed memristor is also included. Furthermore, the non-ideal explanation of the proposed circuits is mathematically examined. The proposed emulators are simulated in SPICE simulator using 180 nm technology. Meminductor circuit and memristor-based low pass filter are used to validate the effectiveness of the designed circuits.

Synthetic Benchmark for Data-Driven Pre-Si Analogue Circuit Verification

As the demand for more complex circuits increases, so does the duration of creating and testing them. The most time-consuming task in circuit development is notoriously the verification process, primarily due to the large number of simulations (hundreds or even thousands) required to ensure that the circuits adhere to the specifications regardless of the operating conditions. In order to decrease the number of required simulations, various verification algorithms have been proposed over the years, but this comes with an additional issue: the thorough validation of the algorithms. As simulations on real circuits are significantly time-consuming, synthetic circuits can offer precious insights into the capabilities of the verification algorithm. In this paper, we propose a benchmark of synthetic circuits that can be used to exhaustively validate pre-silicon (Pre-Si) verification algorithms. The newly created benchmark consists of 900 synthetic circuits (mathematical functions) with input dimensions (variables) ranging from 2 to 10. We design the benchmark to include functions of varying complexities, reflecting real-world circuit expectations. Eventually, we use this benchmark to evaluate a previously proposed state-of-the-art Pre-Si circuit verification algorithm. We show that this algorithm generally obtains relative verification errors below 2% with fewer than 150 simulations if the circuits have less than six to seven operating conditions. In addition, we demonstrate that some of the most complex circuits in the benchmark pose serious problems to the verification algorithm: the worst case is not found even when 200 simulations are used.

Multi-layered computational gene networks by engineered tristate logics

So far, biocomputation strictly follows traditional design principles of digital electronics, which could reach their limits when assembling gene circuits of higher complexity. Here, by creating genetic variants of tristate buffers instead of using conventional logic gates as basic signal processing units, we introduce a tristate-based logic synthesis (TriLoS) framework for resource-efficient design of multi-layered gene networks capable of performing complex Boolean calculus within single-cell populations. This sets the stage for simple, modular, and low-interference mapping of various arithmetic logics of interest and an effectively enlarged engineering space within single cells. We not only construct computational gene networks running full adder and full subtractor operations at a cellular level but also describe a treatment paradigm building on programmable cell-based therapeutics, allowing for adjustable and disease-specific drug secretion logics invivo. This work could foster the evolution of modern biocomputers to progress toward unexplored applications in precision medicine.

An efficient floating point adder for low-power devices

With an increasing demand for power hungry data intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks.

Porous-anodic-alumina-templated Ta-Nb-alloy/oxide coatings via the magnetron-sputtering/anodizing as novel 3D nanostructured electrodes for energy-storage applications

The Ta-52 at.%Nb thin alloy films were magnetron sputter-deposited over a low-aspect-ratio nanoporous anodic-alumina template formed in 0.05 M tartaric acid solution at 250 V and modified by the pore-widening technique to enlarge the pores up to ∼500 nm. The alloy coated the pores evenly, thus forming a 3D continuous conducting nanofilm on the template. Partially anodizing the templated alloy in a borate buffer solution of pH 7.5 generated a compact amorphous mixed-oxide anodic film thickening proportionally to the applied voltage. It was revealed that the oxide on the Ta-52 at.%Nb alloy grows with a slower migration of Ta5+ ions relative to Nb5+ ions, resulting in mixing Ta2O5 and Nb2O5 in the film depth and forming a few-nm-thick Nb2O5 outmost layer. The unique migration of Ta4+, Ta3+, Nb4+, and Nb3+ ions is assumed accountable for forming corresponding suboxides in the 3D anodic film in contrast to a flat Ta-52 at.%Nb alloy film used as a reference. The 3D anodic films behave as an n-type semiconductor with a low donor density Nd = ∼2 × 1018 cm−3, appropriate for dielectric applications. An unusual two-layered structure with a sharp electrical interface revealed in the 3D oxide films anodized to 30–130 V, comprising a low-resistivity layer superimposed on the high-resistivity layer, is explained by an immobile negative space charge in the outer film part. The air-annealing at moderate temperatures releases the space charge and transforms the two layers into a high-resistivity single layer having substantially improved dielectric properties and thermostable (up to 250 °C) capacitance of 1.2 μF cm−2 achieved for the film anodized to practical 50 V. The 3D films having up to 4.5 times enlarged effective surface area can be utilized as novel metal/oxide nanostructured electrodes for electrolytic microcapacitors suitable for classical electronic circuits and energy-storage applications.

Microglia contribute to neuronal synchrony despite endogenous ATP-related phenotypic transformation in acute mouse brain slices

Acute brain slices represent a workhorse model for studying the central nervous system (CNS) from nanoscale events to complex circuits. While slice preparation inherently involves tissue damage, it is unclear how microglia, the main immune cells and damage sensors of the CNS react to this injury and shape neuronal activity ex vivo. To this end, we investigated microglial phenotypes and contribution to network organization and functioning in acute brain slices. We reveal time-dependent microglial phenotype changes influenced by complex extracellular ATP dynamics through P2Y12R and CX3CR1 signalling, which is sustained for hours in ex vivo mouse brain slices. Downregulation of P2Y12R and changes of microglia-neuron interactions occur in line with alterations in the number of excitatory and inhibitory synapses over time. Importantly, functional microglia modulate synapse sprouting, while microglial dysfunction results in markedly impaired ripple activity both ex vivo and in vivo. Collectively, our data suggest that microglia are modulators of complex neuronal networks with important roles to maintain neuronal network integrity and activity. We suggest that slice preparation can be used to model time-dependent changes of microglia-neuron interactions to reveal how microglia shape neuronal circuits in physiological and pathological conditions.