Monolithic 3D Integration Research Articles

Monolithic 3D integration with 2D materials

Monolithic 3D integration with 2D materials

Carrier Mobility Enhancement in Ultrathin-Body InGaAs-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Based on Dual-Gate Modulation

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al2O3 interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 1013 cm−2 was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field.

Self-Aligned Ionic Doping of TiO2 Thin-Film Transistors for Enhanced Current Drivability via Postfabrication Superacid Treatment.

Oxide semiconductor thin-film transistors (TFTs) have shown great potential in emerging applications such as flexible displays, radio-frequency identification tags, sensors, and back-end-of-line compatible transistors for monolithic 3D integration beyond their well-established flat-plane display technology. To meet the requirements of these appealing applications, high current drivability is essential, necessitating exploration in materials science and device engineering. In this work, we report for the first time on a simple solution-based superacid (SA) treatment to enhance the current drivability of top-gate TiO2 TFTs with a gate-offset structure. The on-current of these transistors is limited by the relatively low mobility of TiO2 due to its d-orbital conduction nature. It is found that the on-current of TiO2 TFTs is nearly doubled via a quick dip in a SA solution at room temperature in ambient air. A series of experiments, including comparative I-V measurements of TFTs with different treatments and gate structures, C-V measurements, X-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectrometry, and device simulation, were performed to uncover the underlying reason for the current enhancement. It is believed that the protons (H+) from SA are doped into the offset region of TiO2 TFTs, forming an electron double layer and thus boosting the on-current, with the top gate serving as a self-aligned mask for ionic doping. Furthermore, the ionic size and the proportion of the offset region to the channel play crucial roles in the effectiveness of ionic doping, while the position of the incorporated ions, whether in the channel or dielectric, may result in distinct shifts in the turn-on voltage (VON) and affect the functionality of ionic doping. This study provides a pathway for enhancing the current drivability of TiO2 TFTs via selective ionic doping enabled by SA treatment and deepens our understanding of ion incorporation in electronic devices. This approach could be applicable to other material systems and may also benefit TFTs with miniaturized dimensions, thus opening up unprecedented opportunities for TiO2 TFTs in future applications requiring high current drivability.

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

In this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.

(Invited) 3D Integration of 2D Devices for Neuromorphic Computing

In this presentation, I will delve into the exciting realm of monolithic 3D integration, where emerging 2D FETs take center stage, empowering advanced memory, and logic devices. Furthermore, I will also discuss our work on bio-inspired neuromorphic computing. Notably, our recent breakthroughs have culminated in the successful demonstration of wafer-scale 2-tier and 3-tier 3D integration, utilizing MoS2 and WSe2 FETs as the building blocks. These achievements have paved the way for multifunctional circuits that hold immense promise for the future of electronics. Delving deeper into our research, we have harnessed the potential of 2D materials to design solid-state devices with low power consumption mimicking auditory processing in barn owl, collision avoidance in locust, and probabilistic computing in dragonfly. By combining the power of 2D materials with bio-inspired principles, our work lays a solid foundation for the creation of highly compact and functionally diverse integrated circuits in the revolutionary third dimension. The implications of this technology are far-reaching and hold the potential to shape the future of electronics and computing.

Low-temperature crystallization of BeO-assisted polycrystalline germanium layer for monolithic 3D integration

We demonstrated a new method for the low-temperature solid-phase crystallization (SPC) of germanium on beryllium oxide (BeO) films for monolithic 3D (M3D) integration. Using a wurtzite crystal BeO film, known for its high thermal conductivity of 370 W/m-k at 300 K and covalent bonding characteristics, as the underlying layer, we crystallized Ge at a reduced temperature of 410 °C. For the Ge-on-BeO, the formation of larger grains was consistently promoted at annealing temperatures of 410–500 °C, with a notable 125 % increase in the grain size at 500 °C compared to that at the SiO2 underlayer. The polycrystalline Ge layers crystallized on the BeO retained their tensile strain, as confirmed by the Raman spectra. Furthermore, its optical bandgap of ∼ 1.36 eV and average roughness of 0.847 nm at an annealing temperature of 450 °C make it more suitable for an M3D upper channel layer than Ge-on-SiO2. A comprehensive experimental analysis confirmed the enhanced crystallinity, stability, and channel properties of poly-Ge layers crystallized on BeO. Hence, this study developed a new method for the low-temperature SPC process and highlighted the potential of BeO as a crystallization-assistance thermal-management material for next-generation 3D integrated technology.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

The future of two-dimensional semiconductors beyond Moore's law.

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.

2D materials can unlock single-crystal-based monolithic 3D integration

2D materials can unlock single-crystal-based monolithic 3D integration

Remarkable Bias‐Stress Stability of Ultrathin Atomic‐Layer‐Deposited Indium Oxide Thin‐Film Transistors Enabled by Plasma Fluorination

AbstractA low‐thermal‐budget fabrication approach is developed to realize high‐performance fluorine‐doped indium oxide (In2O3:F) thin‐film transistors (TFTs) with remarkable bias‐stress stability. The ultrathin transistor channel layer is prepared by a re‐developed atomic layer deposition (ALD) process of using cyclopentadienyl indium(I) (InCp) and O2 plasma to deposit a crystalline In2O3 film, followed by a new fluorine doping strategy to use CF4 plasma to afford the In2O3:F layer. As revealed by the density functional theory (DFT) analysis, the fluorine doping can stabilize the lattice oxygen and electrically passivate the problematic VO defects in In2O3 by forming the FOFi spectator defects. Therefore, the fabricated In2O3:F TFTs show simultaneously excellent electrical performance and remarkable bias‐stress stability, with high µFE of 35.9 cm2 V−1 s−1, positive Vth of 0.36 V, steep SS of 94.3 mV dec−1, small hysteresis of 33 mV, and small ΔVth of −111 and 49 mV under NBS and PBS, respectively. This work demonstrates the high promise of the fluorinated ALD In2O3:F TFTs for the CMOS back‐end‐of‐line (BEOL) compatible technologies toward advanced monolithic 3D integration.

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Three-dimensional integration of two-dimensional field-effect transistors.

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as 'More Moore'1 but also introduces multifunctionalities for 'More than Moore'2 technologies. Although silicon-based 3D integrated circuits are commercially available3-5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7-10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.

Reversible Charge Transfer Doping in Atomically Thin In2O3 by Viologens.

Atomically thin oxide semiconductors are emerging as potential materials for their potentiality in monolithic 3D integration and sensor applications. In this study, a charge transfer method employing viologen, an organic compound with exceptional reduction potential among n-type organics, is presented to modulate the carrier concentration in atomically thin In2O3 without the need of annealing. This study highlights the critical role of channel thickness on doping efficiency, revealing that viologen charge transfer doping is increasingly pronounced in thinner channels owing to their increased surface-to-volume ratio. Upon viologen doping, an electron sheet density of 6.8 × 1012 cm-2 is achieved in 2 nm In2O3 back gate device while preserving carrier mobility. Moreover, by the modification of the functional groups, viologens can be conveniently removed with acetone and an ultrasonic cleaner, making the viologen treatment a reversible process. Based on this doping scheme, we demonstrate an n-type metal oxide semiconductor inverter with viologen-doped In2O3, exhibiting a voltage gain of 26 at VD = 5 V. This complementary pairing of viologen and In2O3 offers ease of control over the carrier concentration, making it suitable for the next-generation electronic applications.

(Invited) BEOL-Compatible Oxide Semiconductor Logic and Memory Devices

3D monolithic integration of logic and memory devices has emerged as one of the key enablers for next-generation electronic devices to address the ever-increasing demand for higher integration density, better performance and energy efficiency. BEOL-compatible oxide semiconductors show great potential to revolutionize the field thanks to their unique properties [1].We present our recent advancement related to BEOL-compatible oxide semiconductors for logic and memory applications. The digital-etch-enabled nanowire transistors and α-IGZO-based eDRAM will first be discussed, followed by the ferroelectric (FE) memories with high performance and novel structures utilizing α-IGZO or ALD-deposited ZnO as the channel.Ultra-scaled amorphous IGZO (α-IGZO) nanowire field-effect transistors (NW-FETs) hold great potential for applications demanding high performance and integration density. To realize the fabrication of high-quality and aggressively-scaled nanowire structures, a novel digital etching method for amorphous α-IGZO materials has been proposed and demonstrated [2]. Confirmed by the SEM images of an α-IGZO nanowire before and after digital etching, a notable nanowire width W NW reduction can be observed. We have the thinnest α-IGZO nanowire achieved by the digital etching with a W NW of approximately 20 nm. By further developing the transistor upon the nanowire, the α-IGZO NW-FET attains a good subthreshold swing (SS) of 80 mV/decade and a high peak extrinsic transconductance (G m, ext) of 612 μS/μm at V DS of 2 V (456 μS/μm at V DS = 1 V). Compared to the previous studies, our IGZO NW-FET achieves one of the highest peak G m values among all IGZO-based FETs.Besides the BEOL compatibility and high on-current, ultra-low subthreshold leakage makes α-IGZO FETs extremely promising for eDRAM. We further investigated the potential of α-IGZO eDRAM by developing the charge-domain compute-in-memory (CiM) [3]. Experiments have demonstrated small SS, large on-state current, and long-time charge retention with our dedicated 4T1C memory cell. With differential cell structure, an even higher tolerance for charge loss can be attained. With experiment-calibrated benchmarking in the VGG-8 network for CIFAR-10 image classification tasks, 2092 TOPS/W power efficiency for the CiM core can be expected, outperforming the prior TFT and CMOS-based CiM approaches, exhibiting significant advantages for ultra-low-power applications.The integration of doped-HfO2 FE material and oxide semiconductor, both BEOL-compatible with large-scale and cost-effective deposition, presents a promising avenue for advancing data storage in the future. We have developed the high-performance α-IGZO Fe-FET with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure as well as the Fe TCAM [4]. The α-IGZO Fe-FET achieves a large memory window of ~3 V with high reliability, while the Fe TCAM reduces the transistor number from 16 to 2 compared to the traditional SRAM-based one. Besides α-IGZO, we believe that ALD-based oxide semiconductors featuring high controllability of film thickness and conformal coverage of the 3D structures can create new opportunities for novel device structure and integration. The fin-gate ZnO Fe-FET stands for a great example while not only outstanding device performance but also suppressed device-to-device variation due to the unique structure have been demonstrated, holding tremendous promise for high-density 3D integration [5]. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114).

3차원 집적 유연 인쇄 전자: 집적 회로, 메모리, 센서

Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems

Monolithic 3D (MONO3D) integration provides performance and power efficiency benefits over 2D circuits and, thus, is a potent technology for the design of Deep Neural Network (DNN) accelerators with enhanced energy efficiency. However, high IC temperatures are major challenges for the design of MONO3D systems. To this end, this paper focuses on designing temperature-aware MONO3D DNN accelerators. We propose a new automated method, called TREAD-M3D, that provides a near-optimal MONO3D DNN accelerator architecture in terms of systolic array size, SRAM organization, partition across 3D layers, and operating frequency, for a given DNN, optimization goal, and temperature constraint. TREAD-M3D incorporates circuit-and architecture-level models to evaluate the power and performance characteristics of different partitions. Our method reveals valuable insights and enables tradeoff analysis for achieving high energy efficiency in MONO3D systolic arrays. In comparison to recent works that adopt a fixed partition choice to design MONO3D DNN systems, TREAD-M3D yields up to 22% higher energy efficiency. Using TREAD-M3D, we further demonstrate that temperature unawareness not only leads to infeasible configurations due to temperature violations but also over-estimates energy-delay-product benefits by up to 24%.

High performance junctionless FDSOI SiGe channel p-FinFET with high ION/IOFF ratio and excellent SS

This paper presents a novel FDSOI FinFETs with SiGe channel/Si cap layer (35 nm/5 nm) formed on SOI wafers with 20 nm Si body. Electrical characterization result shows that JL FDSOI FinFETs with SiGe channel exhibited low subthreshold slope (SS) of 86 mV/decade and record high ON-OFF current ratio (ION/IOFF = 2 × 106) at VD = -0.5V, respectively. Device performance improvement was mainly attributed to high-epitaxial quality compressive strained SiGe channel and novel device structure. The strain in the channel of the transistors was estimated locally in TEM using Nano beam diffraction (NBD) technique. The FDSOI FinFET with SiGe channel, lays the foundation for the further development of high speed, high density, low cost, and 3D monolithic integration circuits.

Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions.

Three-dimensional (3D) hetero-integration technology is poised to revolutionize the field of electronics by stacking functional layers vertically, thereby creating novel 3D circuity architectures with high integration density and unparalleled multifunctionality. However, the conventional 3D integration technique involves complex wafer processing and intricate interlayer wiring. Here we demonstrate monolithic 3D integration of two-dimensional, material-based artificial intelligence (AI)-processing hardware with ultimate integrability and multifunctionality. A total of six layers of transistor and memristor arrays were vertically integrated into a 3D nanosystem to perform AI tasks, by peeling and stacking of AI processing layers made from bottom-up synthesized two-dimensional materials. This fully monolithic-3D-integrated AI system substantially reduces processing time, voltage drops, latency and footprint due to its densely packed AI processing layers with dense interlayer connectivity. The successful demonstration of this monolithic-3D-integrated AI system will not only provide a material-level solution for hetero-integration of electronics, but also pave the way for unprecedented multifunctional computing hardware with ultimate parallelism.

Dual-mode distributed feedback quantum cascade laser based on stacked 3D monolithic integration for on-chip multi-channel gas sensing

To facilitate the development of on-chip integrated mid-infrared multi-channel gas sensing systems, we propose a high-power dual-mode (7.01 and 7.5 μm) distributed feedback quantum cascade laser based on stacked 3D monolithic integration. Longitudinal mode control is achieved by preparing longitudinal nested bi-periodic compound one-dimensional Bragg gratings along the direction of the cavity length in the confinement layer. Additionally, transverse coherent coupling ridges perpendicular to the cavity length direction are fabricated in the upper waveguide layer to promote the fundamental transverse mode output when all ridges are in phase. Stable dual-wavelength simultaneous emission with a side-mode suppression ratio of more than 20 dB was achieved by holographic exposure and wet etching. The entire spectral tuning range covers nearly 100 nm through joint tuning of the injection current and heat-sink temperature. High peak power and beam quality are guaranteed by the parallel coherent integration of seven-element ridge arrays. The device operates in a fundamental supermode with a single-lobed far-field pattern, and its peak output power reaches 3.36 W in pulsed mode at 20°C. This dual-mode laser chip has the potential for in-situ on-chip simultaneous detection of CH4 and C2H6 gases in leak monitoring.