Monocrystalline Silicon Carbide Research Articles

Assessment of sustainable and machinable performance metrics of monocrystalline silicon carbide wafer with electrophoretic-assisted multi-diamond wire sawing

Assessment of sustainable and machinable performance metrics of monocrystalline silicon carbide wafer with electrophoretic-assisted multi-diamond wire sawing

Modeling of surface evolution in plasma etching for SiC microgroove fabrication

Monocrystalline silicon carbide (SiC) has attracted attention for applications in devices operating in harsh environments due to its excellent physicochemical properties. However, it is difficult to obtain extremely small-feature sizes with undamaged surfaces due to its extremely high hardness. Herein, a novel method to fabricate SiC microgrooves is proposed that combines molding with inductively coupled plasma (ICP) etching process. First, a Ni–P microgroove master mold was fabricated by ultraprecision cutting and replicated on a polydimethylsiloxane (PDMS) surface, which was then used as the microgroove mold for hot embossing. Then, the patterned mask fabricated by hot embossing was transferred to the SiC substrate by ICP etching. To obtain customized microgrooves, an interface-evolution model based on angular dependence theory was established. A numerical method based on a string algorithm approach is developed for interface-evolution simulations. During ICP etching, the characteristic size d of homogeneous materials and the sidewall angle in heterogeneous materials varied with the sidewall angle of the SU-8 mask due to the angular dependence of etch rate. Finally, seven sets of microgrooves were machined on SU-8 to study the interface-evolution process. Variations in the characteristic size Δd and sidewall angle θ for each unit in homogeneous material, as well as the variations in sidewall angle before and after etching in heterogeneous materials are described. The high accuracy of the proposed interface-evolution model was experimentally validated.

Experimental and Simulation Research on Femtosecond Laser Induced Controllable Morphology of Monocrystalline SiC.

Silicon carbide (SiC) is utilized in the automotive, semiconductor, and aerospace industries because of its desirable characteristics. Nevertheless, the traditional machining method induces surface microcracks, low geometrical precision, and severe tool wear due to the intrinsic high brittleness and hardness of SiC. Femtosecond laser processing as a high-precision machining method offers a new approach to SiC processing. However, during the process of femtosecond laser ablation, temperature redistribution and changes in geometrical morphology features are caused by alterations in carrier density. Therefore, the current study presented a multi-physics model that took carrier density alterations into account to more accurately predict the geometrical morphology for femtosecond laser ablating SiC. The transient nonlinear evolutions of the optical and physical characteristics of SiC irradiated by femtosecond laser were analyzed and the influence of laser parameters on the ablation morphology was studied. The femtosecond laser ablation experiments were performed, and the ablated surfaces were subsequently analyzed. The experimental results demonstrate that the proposed model can effectively predict the geometrical morphology. The predicted error of the ablation diameter is within the range from 0.15% to 7.44%. The predicted error of the ablation depth is within the range from 1.72% to 6.94%. This work can offer a new way to control the desired geometrical morphology of SiC in the automotive, semiconductor, and aerospace industries.

Solid and Liquid State Dewetting of Thin Silicon Films Sandwiched between Two Silicon Carbide Substrates

Silicon carbide (SiC) is a very promising material for power electronics thanks to its wide band gap and high thermal conductivity. Stacking of SiC substrates of different crystalline quality and/or doping levels through wafer bonding is of particular interest for applications. Although a direct SiC/SiC bonding may result in an unstable interface, a layer of intermediate material playing a role of a “glue” can be sandwiched between the SiC substrates to ensure their good attachment. However, the processing of the power electronics devices at a high temperature may degrade the properties of this material which evolution under high temperature annealing must be studied in advance.In this work, we exploited the possibility to use silicon (Si) as a bonding material. We studied the structure evolution of a nanometer-thick polycrystalline Si layer sandwiched between two monocrystalline SiC substrates with a high temperature annealing. We focused our attention on understanding the impact of as-bonded Si layer thickness and the temperature of annealing on the eventual Si layer morphology. Tests were conducted for Si films of as-bonded thickness of 8 nm, 20 nm and 40 nm at temperatures ranging from 950°C to 1400°C, i.e. below Si melting temperature of 1414°C, and above it up to 1700°C. The experiments were realized using transmission electron microscopy (TEM), scanning electron microscopy (SEM) and high-resolution X-ray diffraction techniques. Cross-sectional TEM images were used to describe the structure and morphology of the interface. SEM was used to observe the inner surface of one of the SiC substrates once the other was removed by a cleavage. X-ray measurements were carried out to determine Si film thickness and texture as well as the strain in Si and SiC.We show that annealing at temperatures ranging from 950°C to 1400°C results in pitting, i.e. creation of voids, at the Si/SiC interfaces which are observed for any studied as-bonded thickness of a Si layer. We attribute this effect to a solid state dewetting of Si from SiC. This dewetting effect evolves into complete piercing of the silicon film and formation of cylindrical voids within the Si layer which grow in diameter with annealing temperature. We also observe a thickening of the silicon layer. The driving force for a solid state dewetting will be discussed in terms of SiC/Si interface energy, vacancies precipitation and Si atoms diffusion.When annealed to relatively higher temperatures allowing for Si melting followed by its solidification, we put into evidence the formation of step bunching on the internal surfaces of both SiC substrates. Regarding Si, it is concentrated along the SiC steps. The mechanism of the reconstruction of SiC internal surfaces resulting in the creation of step bunching will be discussed in relation to Si liquid state dewetting, carbon atoms dissolution, recondensation and migration within liquid Si.The effect of as-bonded silicon film thickness on the Si dewetting process is not pronounced after annealing at 950°C: all samples contain pits of a similar size and density. When the annealing temperature is slightly increased above 1000°C, the pits in the Si films of a lower initial thickness transform into cylindrical voids piercing the layers. The thicker layers contain both pits and cylindrical voids. At a high enough temperature of 1400°C only cylindrical voids were observed in all samples. The thicker layers present the lowest densities of voids.For the annealing at temperatures higher than 1400°C, the as-bonded thickness of a Si layer had a direct impact on the height of the steps formed on the internal surfaces of the SiC substrates. The eventual steps were higher the thicker the Si layer was used for bonding.The role of the diffusion and interaction of Si and C atoms and vacancies during annealing will be discussed in relation to the dynamics of solid and liquid state Si dewetting, size and density of pits and cylindrical voids and eventual Si layer morphology.Figure 1, on the left, SEM images showing the evolution of Si solid state dewetting with annealing temperature, from pitting to the formation of cylindrical voids. On the right, SEM and cross-sectional TEM images showing the step bunching on the SiC internal surfaces and the Si accumulation at the steps obtained after Si liquid state dewetting. Figure 1

Microscopic stress analysis of nanoscratch induced sub-surface defects in a single-crystal silicon wafer

The existing stress criterion assumes the material to be isotropic and only distinguishes elastic, plastic, and crack zones, to explain the scratching-induced sub-surface defects during the contact loading processes such as nanoindentation, nanoscratching, and grinding. However, anisotropic single-crystal materials such as monocrystalline silicon and silicon carbide have more diverse defect characteristics and sub-surface defects in these materials cannot be well explained and predicted using the existing criterion. In this study, a thorough microscopic characterisation and complementary stress analysis were performed on a single-crystal silicon wafer during nanoscratching. A novel criterion based on mechanism of dislocation multiplication and propagation was proposed and validated, providing a better understanding of sub-surface defects prediction in silicon. Compared to conventional sub-surface defects models, this new shear stress-based criterion can accurately predict the position and extent of dislocations in silicon. The dislocations layout for scratching along any direction on the (100) surface of Si were further discussed to offer a comprehensive understanding of the effect of anisotropic structure of single-crystals on the sub-surface defects. The improved understanding of inelastic deformation in single-crystal silicon, which was revealed by this new model, will have a significant impact on the nanomanufacturing sector by guiding the contact mode experiments (grinding, indentation, machining) towards efficient machining.

Study on warpage and filling behavior of glass in non-isothermal hot embossing

Non-isothermal hot embossing has great potential in the mass production of glass micro optical components due to the relatively short heating-cooling cycle time. However, warpage was induced by the temperature gradient inside the glass replica during hot embossing, resulting in a deteriorated optical performance. Therefore, it is non-trivial to investigate the effects of process parameters on warping and filling behaviors of glass in non-isothermal hot embossing. Firstly, a high-quality microhole was fabricated on monocrystalline silicon carbide (SiC) mold by focused ion beam (FIB) lithography. By using a novel home-made gravity-assisted hot embossing machine, the geometric information (i.e., warpage and microstructures) on SiC mold was transferred into the surface of N-BK7 glass replica. The experimental results indicate that high embossing temperature enables not only the minimization of warpage but also the enhancement of microstructure replication accuracy. Furthermore, increasing embossing force enhances filling capacity but increases warpage amplitude. Interestingly, fast heating/cooling rates and short embossing time enable a small warpage as well as a high embossing efficiency. By optimizing the process parameters, especially the embossing temperature, a small warpage amplitude of 3 μm and a high transfer ratio of 99.11% were achieved, which can meet the high requirement of precision optical components.

Study on surface roughness of monocrystalline silicon carbide based on PSD evaluation and pseudo-random tool path

Study on surface roughness of monocrystalline silicon carbide based on PSD evaluation and pseudo-random tool path

Molecular dynamics study on grinding mechanism of polycrystalline silicon carbide

In this paper, stress, temperature, dislocation, surface morphology and crystal structure of polycrystalline silicon carbide under different grinding speeds and grain sizes are studied by molecular dynamics simulation. Influence of silicon carbide with different grain sizes on formation and emission of dislocations and relationship between formation and emission of dislocations under different grinding speeds are revealed. By comparing number of amorphous atoms and generation of dislocations between monocrystalline silicon carbide and polycrystalline silicon carbide at different grinding speeds, it is observed that thickness of subsurface damage layer of monocrystalline silicon carbide correspondingly increases with grinding speed. In contrast, damage layer of polycrystalline silicon carbide is determined by the joint action of grain size and grinding speed, and it does not decrease with increase in grinding speed, unlike monocrystalline silicon carbide. Accumulation of dislocations at the grain boundary causes strengthening between the grain boundaries, and alters the cutting force. In the grinding process, although grinding speed is not the primary factor affecting surface topography, it is the main factor affecting workpiece temperature.

Simulation and experimental study on limited cutting and heat effect of silicon carbide

As a typical third-generation semiconductor material, silicon carbide (SiC) presents outstanding properties in terms of the bandgap width, disruptive voltage strength, thermal conductivity and so on. However, there are still technical difficulties in acquiring the nondestructive surface with an optical quality, which seriously constrained the application and development of SiC functional devices. Therefore, in this paper, the material removal mechanism of SiC was firstly investigated according to the MD simulation results. Then, nanocutting experiments were conducted under the vacuum environment of the scanning electron microscope, where the transient behavior of material removal could be observed online with a high resolution, so that the simulation results can be effectively verified. From the simulated and experimental results, it was found that under the research range of parameters, the limited removal thickness (LRT) of SiC decreased with an increase in cutting speed, while the cutting depth had little effect on the LRT. Besides, the polycrystalline SiC presented a smaller LRT compared with the monocrystalline SiC. Therefore, it was advantageous to enhance the machined surface quality and improve the surface integrity with regard to polycrystalline SiC. The cutting temperature increased with an increase in cutting speed during the nanocutting, and a higher cutting speed can prolong the time for the workpiece temperature to stabilize. The findings of this study are able to provide a theoretical basis for the improvement of ultraprecision machining technology especially for hard–brittle and hard-to-process materials. • Material removal mechanism was studied both experimentally and numerically. • Limited removal thickness was studied by labeling and tracing the silicon atoms. • Nanocutting tests were performed with online observation via an SEM. • Experimental results are in good agreement with the MD simulation results.

Molecular Dynamics Simulation of Nanomachining Mechanism between Monocrystalline and Polycrystalline Silicon Carbide

AbstractAs an advanced ceramics material, silicon carbide (SiC) is extensively applied in numerous industries. In this study, molecular dynamics method is used to comparatively investigate the nanomachining mechanism between monocrystalline SiC (mono‐SiC) and polycrystalline SiC (poly‐SiC) ceramics. Four simulations are performed for the two materials with and without ultrasonic vibration‐assisted machining (UVAM). The diamond tool is set as a non‐rigid body and vibrated along the depth direction with 100 GHz in frequency and 0.5 nm in amplitude. The effects of material and ultrasonic vibration on the nanomachining mechanism of SiC are analyzed in depth, including the surface generation, subsurface damage, and tool wear. It is determined that the machinability of SiC ceramics can be effectively improved by UVAM. The machining‐induced damage extent of poly‐SiC is more serious than that of mono‐SiC. It is also found that UVAM can effectively reduce the machining‐induced damage, decrease the machining resistance, and increase the possibility of ductile removal, but bring about a slightly larger tool wear.

Механические свойства композитного покрытия SiC на графите, полученного методом замещения атомов

The mechanical properties of composite coatings made of silicon carbide on graphite are studied for the first time. For the deposition of coatings, a new method of annealing the initial graphite was used, which was in contact with a silicon melt in an atmosphere of carbon monoxide.The samples were studied by nanoindentation and scanning electron microscopy. It is shown that the formed coating consists of a continuous film of monocrystalline silicon carbide lying on the surface, dendrites and crystalline druses, with roots going deep into the sample through a system of pores. It is shown that the coating significantly increases the mechanical characteristics of the graphite surface, including the microhardness.

Tribo‐mechanical properties of composites based on polyoxymethylene reinforced with basalt fiber andsilicon carbidewhiskers

AbstractThis paper presents an analysis of the hybrid reinforcement of polyoxymethylene composites. Basalt fibers and monocrystalline silicon carbide fibers were used as reinforcement. Basic tests of mechanical properties were carried out, such as the static tensile and flexural test. The tests were repeated under external factors, such as the influence of water aging and a wide range of exploitation temperatures. The materials were also subjected to tribological tests, that is, determination of the friction coefficient and the specific wear rate. Strength tests revealed an increase in the stiffness of the material as well as a reduction the friction coefficient and abrasive wear. The addition of monocrystalline fibers significantly limited water absorption, stabilized the strength properties in the water environment as well as provided better material's resistance to dynamic impact.

Анализ эпитаксии карбида кремния из газовой фазы как базового процесса в техно-логии силовой электроники. Обзор

Currently, chemical gas deposition is the main method for producing high-quality and reproducible epitaxial layers for commercial silicon carbide (SiC) power devices. Based on the experience of ETU «LETI» in the synthesis of monocrystalline SiC, an analysis of the current state of silicon carbide gas phase epitaxy (CVD) technology was carried out. It has been shown that modern CVD reactors allow to implement the growth processes of SiC epitaxial structures of high quality with the following parameters: substrates diameter up to 200 mm; thicknesses of epitaxial layers from 0.1 to 250 μm; layers of n - and p -types conductivity with ranges of doping levels 10-10 cm and 10-10 cm, respectively. At the same time, setting up the technology of the reproducible high-quality growth of epitaxial layers is an individual task for a specific type of reactor. It requires a detailed consideration of the technological factors presented in this paper, which at the end determine the achievable parameters of SiC-epitaxial products

Cost-Efficient High-Throughput Polishing of Silicon Carbide Seed Crystals

Polishing of Silicon Carbide (SiC) seed crystals and substrates to achieve an extremely smooth, level surface, and an optically clear finish takes many surface finishing steps with very long processing times producing a significant amount of slurry waste and utilizing numerous lapping and polishing machines. This paper presents a newly developed cost-efficient SiC polishing process which reduces these operations to two surface finishing steps for achieving an optically clear finish on monocrystalline SiC material where the same size of diamond abrasives for lapping and polishing steps allows to carry out stock removal lapping and polishing processes on a single platform (machine) without concern of cross-contamination and making it as a very cost-efficient and high-throughput polishing process for SiC seed crystals and substrates.

Mechanism of the scratching of monocrystalline silicon carbide with a diamond grit at different wear stages

An investigation was conducted to explore the mechanisms of the scratching of monocrystalline silicon carbide with a single diamond grit. The scratching was repeated on a silicon carbide workpiece to generate different wear shapes of the diamond grit. The forces were recorded during each scratching and the wear of the diamond grit together with the silicon carbide morphologies was monitored at a fixed interval. Based on the different diamond wear shapes determined through scratching experiments, a smoothed particle hydrodynamics method was used to simulate the scratching process. In addition to the items monitored in the experiments, the simulation was also used to analyze the change of subsurface damages on silicon carbide and to predict the mechanisms of diamond damage. It is shown that double-edged abrasive grits might lead to a better silicon carbide surface quality in scratching. The simulation results indicate that the maximum equivalent stress distribution might be used to predict the damage of the diamond grits during scratching. The findings of this article will be of benefit to the optimal selection of machining parameters and the optimal design of diamond tools for abrasive machining of monocrystalline silicon carbide.

(Invited) Nano-Precision Deep Reactive Ion Etching of Monocrystalline 4H-SiCOI for Bulk Acoustic Wave Resonators with Ultra-Low Dissipation

Introduction Micromechanical resonators with ultra-low energy dissipation are essential for a wide range of applications, including chemical sensors, and inertial sensors for navigation in GPS-occluded environments [1]. While ease of batch fabrication along with high-fidelity wafer-level processing have made monocrystalline silicon (Si) the preeminent substrate for seamlessly integrated microelectromechanical systems (MEMS), Si may not be suited to address the ever-growing demand for high-precision MEMS instruments robust to harsh environments. As the quest for low dissipation is plateauing with the direct observation of Si’s quantum limit, monocrystalline Silicon Carbide (SiC) is under active investigation for its promise of room-temperature mechanical Qs exceeding 100M at 6 MHz, owing to its extraordinary Akhiezer damping, which sits 30x below that of Si. Such high Qs are critical to demonstrate navigation-grade resonant gyroscopes with Angle Random Walk (ARW) near 0.00017°√hr, matching the performance of ring laser gyroscopes while being potentially vastly more portable and affordable. Ultra-low Dissipation SiC Resonators This paper reports on the implementation of capacitive SiC resonators with micron-scale transduction gaps, exhibiting fQ=1.25x1014 Hz, a 5-fold improvement over Si’s limits which has already been reported in [3]. These results are particularly interesting because SiC is more susceptible to thermoelastic damping (TED) than Si, by a factor near 5x. To break through the barrier set by material properties that grant an inferior Q TED limit, we have fabricated clamped-clamped beam [4], bulk acoustic wave (BAW) disk [5-6], and Lamé mode resonators [3] using high-density plasma etching of monocrystalline 4H-SiC-on-Insulator (SiCOI) fusion-bonded substrates in STS AOE. We have experimentally verified that these resonators have a decreasing susceptibility to TED in accordance with COMSOL simulations. While the volume-preserving Lamé mode is virtually TED-free in a tether-less square configuration, the unavoidable introduction of tethers and sidewall roughness due to the finite precision of deep reactive ion etching (DRIE) of SiC exacerbates TED. Method While the overarching fabrication details have been published elsewhere [3-6], the SiC DRIE optimization in STS AOE is presented here for the fist time. Plasma etching of SiC can be accompanied by the undesired formation of micropillars because the metallofluorinated NiCxFy compound accumulates on the sidewall and flakes off under various conditions. This issue is circumvented by tailoring the DRIE recipe to reduce the growth rate of the passivation layer. With that in mind, we typically flow an excess of Ar compared to SF6 to starve the trenches from F-based species that tend to polymerize with exposed C atoms. We optimize the coil and platen power to generate a self-bias DC voltage of nearly 280V and reduce the pressure to 8mTorr to prevent any sidewall damage due to the lack of passivation on the sidewall. Results and Conclusions Fig. 1 reveals that selecting bulk acoustic wave (BAW) mode resonators and operating deep in their adiabatic regime enables to the barrier set by TED in monocrystalline SiC, unlike for flexural resonator that operate near the Debye peak. However, surface TED can still limit Q if asperities form on the sidewall of the SiC BAW resonators; we prevent their formation by tailoring the DRIE recipe to limit the deposition of the NiCxFy passivation and by intermittently removing the passivation in wet etchants (Fig. 2). Moreover, removing the passivation enables to etch high-aspect-ratio trenches in SiCOI wafers with nanoscale smoothness (Fig. 3). By designing acoustically deaf SiC Lamé resonators [3], we reveal that SiCOI substrates can support ultra-low dissipation resonators, which fQ=1.25x10 14 Hz, 5x improvement over the limit of monocrystalline Si (Fig. 4). Through the development of nano-scale precision SiC DRIE, this paper opens the door to a myriad of high-performance chip-scale SiC instruments that can be deployed in harsh environments.

Experimental investigation of semiconductor structures of the power source based on carbon-14

The article presents the research results of semiconductor silicon carbide (porous) structures with the implanted carbon-14. The results of experimental measurements collected data on parameters of photovoltaic energy conversion of light quanta into a photo-EMF to confirm the efficiency of p-n junction, an evaluation of the effectiveness of the introduction of carbon-14 in the molecule silicon carbide electrophysical measurements. In the process used the technology of solid-phase transformation of the surface of the monocrystalline silicon substrate in the phase of monocrystalline silicon carbide by chemical transport of carbon in the environment of hydrogen.

Study of the effect of substrate holder temperature on the etching rate of monocrystalline silicon carbide

The paper touches upon the features of thermal stimulated plasma chemical etching (PCE) 6H-SiC in fluorine-containing inductively coupled plasma (ICP) in the temperature range from 50 °C to 300 °C. It was found that the etching rate of silicon carbide increases linearly from 0.9 µm/min to 1.3 µm / min with an increase in the temperature of the substrate holder from 50 °C to 150 °C, and further temperature increase to 300 °C does not contribute to an increase in the etching rate of SiC. On the basis of the obtained experimental data, the physicochemical regularities of plasma chemical etching of silicon carbide at elevated values of the substrate temperature were determined.

A Novel Method of Synthesizing Graphene for Electronic Device Applications.

This article reports a novel and efficient method to synthesize graphene using a thermal decomposition process. In this method, silicon carbide (SiC) thin films grown on Si(100) wafers with an AlN buffer layer were used as substrates. CO2 laser beam heating, without vacuum or controlled atmosphere, was applied for SiC thermal decomposition. The physical, chemical, morphological, and electrical properties of the laser-produced graphene were investigated for different laser energy densities. The results demonstrate that graphene was produced in the form of small islands with quality, density, and properties depending on the applied laser energy density. Furthermore, the produced graphene exhibited a sheet resistance characteristic similar to graphene grown on mono-crystalline SiC wafers, which indicates its potential for electronic device applications.

SEMI Standards for SiC Wafers

SEMI Standards charter is to develop standards that benefit the semiconductor industry. The SEMI organization has evolved over the last 40 years into an international organization with covering all aspects of semiconductor and flat panel materials and devices. SEMI Standards provides the framework for the development of consensus based standards documents. At present there are two published standards specific to silicon carbide, the first dealing with dimensions, properties and ordering information for SiC wafers, and the second defining a nomenclature for defects found on SiC: SEMI M55-0817 Specification for Polished Monocrystalline Silicon Carbide Wafers SEMI M81-0611 Guide to Defects Found on Monocrystalline Silicon Carbide Substrates Additional standards applicable to various semiconductor wafers also are available and new SiC related standards are being developed based on industry needs and volunteer participation.