Molecular Beam Epitaxy Chamber Research Articles

Nature of contaminants introduced in silicon wafers during molecular beam epitaxy chamber annealing

Epitaxial monolithic III–V/Si tandem solar cells are one of the most promising technologies to be adopted by the industry after the efficiency of the current market dominating single junction silicon solar cell saturates at its fundamental limit. One of the key limitations of this technology is the degradation of silicon wafers during in situ annealing in the molecular beam epitaxy chamber. Determining the nature of contaminants in this process is key to improve the efficiency of epitaxial tandem solar cells. However, to date, the nature of contaminants from molecular beam epitaxy chambers remains unknown. In this work, we use photoluminescence imaging, lifetime spectroscopy, and deep level transient spectroscopy to measure the electronic properties of extrinsic impurities incorporated during annealing in the molecular beam epitaxy chamber. Photoluminescence images reveal that at least two impurities diffuse into silicon wafers during molecular beam epitaxy annealing. One is highly localized, while the other one is distributed uniformly across the whole wafer. Phosphorus diffusion is found to confine the localized impurity within the diffused layer but is ineffective at preventing the indiffusion of other impurities. Lifetime spectroscopy shows that metastable impurities with characteristic similar to Cr and CrB in our molecular beam epitaxy annealed silicon wafers. No evidence of Fe or FeB was observed. The emission rates and concentrations of the electrically active defects were measured with deep-level transient spectroscopy: The emission rates of detected defects do not match that of known Cr-related defects.

Growth of 28Si Quantum Well Layers for Qubits by a Hybrid MBE/CVD Technique

Isotopically enriched 28Si quantum well layers in SiGe/Si/SiGe heterostructures are an excellent material platform for electron spin qubits. In this work, we report the fabrication of 28SiGe/28Si/28SiGe heterostructures for qubits by a hybrid molecular beam epitaxy (MBE) / chemical vapour deposition (CVD) growth, where the thick relaxed SiGe substrates are realised by a reduced-pressure CVD and the 28SiGe/28Si/28SiGe stacks are grown by MBE Here, we achieve a fully strained 28Si quantum well layer in such heterostructures with a 29Si concentration as low as 200 ppm within the MBE grown layers. It concludes that 29Si primarily originates from the residual natural Si vapour in the MBE chamber. A reliable surface preparation combining ex situ wet chemical cleaning and in situ annealing and atomic hydrogen irradiation offers epitaxy ready CVD grown SiGe substrates with low carbon and oxygen impurities. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. It shows that the misfit dislocation formation is significantly suppressed at a low MBE growth temperature, such as 350 °C.

Microscopic Views of Ge Segregation and Scavenging Ge on Thin Si on Epi-Ge(001)

Si capping layer is the most notable approach used in Ge metal-oxide-semiconductor (MOS);1-2 however, the Ge segregation and diffusion occurred during the growth of Si.3-4 The formation of undesirable GeOx is detrimental to the Ge nMOS reliability.5 This work focuses on using the scavenging process to reduce the segregated Ge atoms and to completely remove GeOx in the high-k/epi-Si/epi-Ge(001). We used high-resolution synchrotron radiation photoelectron spectroscopy (SRPES) to show the detailed development of Ge segregation and scavenging Ge using in-situ film growth, oxidation, and annealing. The Si films in 8Å thickness were grown on the epi-Ge(001) in a semiconductor molecular beam epitaxy (MBE) chamber.2 These samples were in-situ transferred to National Synchrotron Radiation Research Center in Taiwan for electronic structure studies using photoemission. Molecular oxygen was exposed to the epi-Si/epi-Ge(001) surfaces at 300°C in the photoemission chamber. The samples were then in-situ annealed at 500°C for 5 min under an ultra-high vacuum (UHV).The topmost surface of epi-Ge(001) is terminated with Ge-Ge buckled dimers.6 In the case of room-temperature grown amorphous Si (a-Si) film, the intensity of the Ge down-dimer component from the underlying epi-Ge remains as it is. The Ge up-dimer atoms were partly diffused into the a-Si film, and some of them were segregated to the top of the a-Si surface. The epi-Si grown at 260 - 280°C causes the rest of the Ge down-dimer atoms to move to the epi-Si surface to become both segregated Ge (segGe) and diffused Ge (diff-Ge). The growth of Si merely affects the topmost surface, and the Ge atoms in the second layer of the epi-Ge remain intact. A comparison of the amount of GeOx for HfO2/epi-Si/epi-Ge(001) and HfO2/epi-Ge(001) shows that the epi-Si has greatly reduced the amount of GeOx. However, the GeOx, segGe and diff-Ge components are still observed in the HfO2/epi-Si/Ge(001) samples.We have previously reported that three-time scavenging cycles have greatly reduced the amount of segGe and diff-Ge atoms in high-κ/epi-Si/n-Ge(001), thus decreasing electron traps.7 Each scavenging cycle includes room-temperature oxidation followed by thermal annealing. In this study, the oxidation of the as-grown epi-Si/epi-Ge(001) samples was performed at 300°C. It is worth noting that there is no GeOx formation on the surface after the thermal oxidation, which is different from the room-temperature oxidation of the epi-Si/epi-Ge(001) surfaces. In addition, the oxidation at 300°C affects part of the diff-Ge atoms to evaporate from the surface, which is also different from our previous work, where the diff-Ge component shows no change in intensity since the oxidation occurred at room temperature. The subsequent in-situ annealing at 500°C moved the residual Ge-boned Si (diff-Ge) inside the epi-Si to the surface to become part of the segGe atoms. In conclusion, we have used the aforementioned process to further reduce the segregated Ge, and thus the GeOx, on top of the epi-Si/epi-Ge(001).To whom the correspondence is addressed: mhong@phys.ntu.edu.tw (M. Hong), raynien@phys.nthu.edu.tw (J. Kwo), and pi@nsrrc.org.tw (T. W. Pi)AcknowledgmentsThis work is supported by MOST 110-2112-M-002-036-, 110-2622-8-002-014-, 110-2923-M-002-001-, and 110-2112-M-213-012- of the Ministry of Science and Technology in Taiwan.Reference 1 H. Arimura, E. Capogreco, A. Vohra, C. Porret, R. Loo, E. Rosseel, A. Hikavyy, D. Cott, G. Boccardi, L. Witters, G. Eneman, J. Mitard, N. Collaert, and N. Horiguchi, IEEE Int. Electron Devices Meet., 2.1.1−2.1.4 (2020). 2 H. W. Wan, Y. J. Hong, Y. T. Cheng, C. K. Cheng, C. H. Hsu, C. T. Wu, T. W. Pi, J. Kwo, and M. Hong, M., ACS Appl. Electron. Mater. 3, 2164−2169 (2021). 3 R. Loo, H. Arimura, D. Cott, L. Witters, G. Pourtois, A. Schulze, B. Douhard, W. Vanherle, G. Eneman, O. Richard, P. Favia, J. Mitard, D. Mocuta, R. Langer, N. Collaert, ECS J. Solid State Sci. Technol. 7, 66−72 (2018). 4 Y. T. Cheng, H. W. Wan, C. K. Cheng, C. P. Cheng, J. Kwo, M. Hong, T. W. Pi, Appl. Phys. Express 13, 085504 (2020). 5 J. Franco, B. Kaczer, P. J. Roussel, J. Mitard, S. Sioncke, L. Witters, H. Mertens, T. Grasser, G. Groeseneken, IEEE Int. Electron Devices Meet., 15.2.1−15.2.4 (2013). 6 Y. T. Cheng, Y. H. Lin, W. S. Chen, K. Y. Lin, H. W. Wan, C. P. Cheng, H. H. Cheng, J. Kwo, M. Hong, T. W. Pi, Appl. Phys. Express 10, 075701 (2017). 7 Y. T. Cheng, H. W. Wan, T. Y. Chu, T. W. Pi, J. Kwo, M. Hong, ACS Appl. Electron. Mater. 3, 4484-4489 (2021).

Selective area epitaxy of PbTe-Pb hybrid nanowires on a lattice-matched substrate

Topological quantum computing is based on braiding of Majorana zero modes encoding topological qubits. A promising candidate platform for Majorana zero modes is semiconductor-superconductor hybrid nanowires. The realization of topological qubits and braiding operations requires scalable and disorder-free nanowire networks. Selective area growth of in-plane InAs and InSb nanowires, together with shadow-wall growth of superconductor structures, have demonstrated this scalability by achieving various network structures. However, the noticeable lattice mismatch at the nanowire-substrate interface, acting as a disorder source, imposes a serious obstacle along with this roadmap. Here, combining selective area and shadow-wall growth, we demonstrate the fabrication of PbTe-Pb hybrid nanowires - another potentially promising Majorana system - on a nearly perfectly lattice-matched substrate CdTe, all done in one molecular beam epitaxy chamber. Transmission electron microscopy shows the single-crystal nature of the PbTe nanowire and its atomically sharp and clean interfaces to the CdTe substrate and the Pb overlayer, without noticeable inter-diffusion or strain. The nearly ideal interface condition, together with the strong screening of charge impurities due to the large dielectric constant of PbTe, hold promise towards a clean nanowire system to study Majorana zero modes and topological quantum computing.

Repeatability and Mechanisms of Threading Dislocation Reduction in InN Film Grown with In Situ Surface Modification by Radical Beam Irradiation

The objective of this study was to investigate the repeatability of in situ surface modification by radical beam irradiation to reduce threading dislocation density in InN film. The growth of InN template and N radical irradiation processes were repeated twice in situ in the radio-frequency plasma-excited molecular beam epitaxy chamber before the regrowth of InN film on the N radical irradiated template. Transmission electron microscopy was applied to study dislocation behaviors of the InN film grown. In this letter, we show cross-sectional-view transmission electron microscopy evidence of the threading dislocation reduction from ~2.8×1010 cm-2 in the first irradiated InN layer to ~2.0×1010 cm-2 in the second irradiated InN layer, and to ~1.3×1010 cm-2 in the top regrown InN layer. The mechanisms of threading dislocation reduction were also studied.

Epitaxial Growth of Highly Sb-Doped Ge on p-Ge (100) for Vertical Transistor Applications

In recent years, Ge-based semiconductor materials has attracted a lot of attention for its possibility of higher mobility channel formation, toward next-generation complementary metal-oxide-semiconductor (CMOS) transistors. For this material to reach its potential, formation and optimization of p-n junction, which is the fundamental structure for a practical device, need to be investigated. In most cases, dopant ions are injected to form dopant-enriched films at the semiconductor interface, followed by annealing with various possible techniques1. However, crystal damages caused by high implantation energy makes it difficult to recrystallize and activate the dopant atoms. In this research, in-situ doping of Sb in epitaxial Ge layers grown on crystalline p-Ge substrates were studied, aiming a vertical p-n diode with higher Sb doping while maintaining good crystal quality. Formation of highly doped n-Ge is one of the most crucial challenges, as it was reported that uniform doping distribution across the layers are difficult to be achieved, which potentially deteriorate the crystallinity of the n-Ge layer2,3. Therefore, a study to overcome the doping problems in n-Ge, can lead to wider application of Ge-based devices.The p-Ge substrates were treated by ultrasonic cleaning in Acetone followed by a diluted-HF dip and de-ionized water rinse. The cleaned substrate then loaded into molecular beam epitaxy (MBE) chamber (base pressure of 10-8 Pa) and subjected to thermal cleaning at 450 ºC for 10min. Subsequently, Ge film were homo-epitaxially grown on the p-Ge substrate using the Knudsen cell (K-cell) that heated around 1100 ºC to maintain a fixed 0.2 Å/s deposition rate. At the same time Sb source was evaporated by heating the Sb K-cell (Tdop.: 325-400 ºC) for the in-situ doping deposition. Here, the depositions of Sb-doped Ge layer were performed on the p-Ge substrate at fixed temperature of 450 ºC. The Sb contents in the epitaxial layer were quantitatively evaluated by the secondary ion mass spectrometry (SIMS), and a reflection high-energy electron diffraction (RHEED) system equipped on the MBE chamber was used to monitor the epitaxial growth during depositions. Moreover, the crystal quality also characterized by the Raman spectroscopy method. After the deposition of 100 nm Sb-doped Ge layer, the samples then used to form vertical p-n diode structures using a conventional lithography method as shown in Fig. 1.The depth profiles obtained by SIMS measurements shows that high amount of Sb atoms (>1019 cm-3) was incorporated into the epitaxial Ge layer (Fig 2(a)). It also shows that Sb atomic concentrations vary with the Sb K-cell temperatures (Tdop.), in which higher temperature (Tdop.: 400 ºC) resulted in higher Sb concentration. The epitaxial growth of Sb-doped Ge layer was observed using the RHEED system, which resulted in a streaky pattern of the diffracted electron beam as seen in the inset of Fig. 2(b). The crystallinity of the epitaxial layer also matched with the results obtained by of Raman measurement shown in Fig.2(b). A strong Ge-Ge phonon peak at similar position to the reference crystalline Ge (at 300.2 cm-1) was obtained for both Tdop.: 325 ºC and 400 ºC samples. This result indicates the growth of Ge crystals with high crystallinity despite the high Sb content. Fig. 2(c) shows rectifying properties for vertical p-n junctions using these samples, where the current obtained at forward bias is much higher than that obtained at reverse bias (ION >> IOFF ). Interestingly, this p-n diode rectifying behavior was also improved (higher ION /IOFF ratio) with the increase of dopant concentrations. The relation between Sb concentration and electrical properties can be explained by the dopant activation rate in the Sb-doped Ge layer, because higher amount of Sb atoms increases the electron doping density. This result clearly shows that highly doped n-Ge layer was formed on the top of p-Ge. This can be expected a useful method for the formation of next-generation vertical transistors where n+-Ge is utilized in source/drain formation. Further investigation about the growth conditions and its relations with electrical properties of the vertical p-n diodes will be discussed in the main presentation. References Sgourou, E. N., Panayiotatos, Y., Vovk, R. V., Kuganathan, N. & Chroneos, A. Diffusion and dopant activation in germanium: Insights from recent experimental and theoretical results. Appl. Sci. 9, (2019).Yurasov, D. V. et al. Antimony segregation in Ge and formation of n-type selectively doped Ge films in molecular beam epitaxy. J. Appl. Phys. 118, (2015).Sawano, K. et al. Ultrashallow Ohmic contacts for n-type Ge by Sb δ -doping. Appl. Phys. Lett. 97, 2008–2011 (2010). Figure 1

Intermittent growth for InAs quantum dot on GaAs(001)

We performed an intermittent growth of InAs quantum dots (QD) on GaAs(001) at 500 °C. The transition of surface structures during the growth was investigated by using reflection high energy electron diffraction observation. We also performed in situ observation of QD nucleation by using STMBE system in which a scanning tunneling microscope equipped within a molecular beam epitaxy chamber. We have found that the initial QDs formation occurred from 1.15 to 1.38 ML with the intermittent InAs supply. This InAs supply amount was much smaller than that of ordinary continuous deposition (∼1.66 ML). Moreover, the QDs mainly appeared on the terrace while they mainly appear on step edges by continuous growth at 500 °C. This indicates that the annealing parts of the intermittent growth affected the surface atomic structures of InGaAs wetting layer, uniforming the In fluctuation and stabilized the surface morphology. By the preparation of large (n×3) and (2×4) area, the QD nucleation occurs with a smaller InAs supply on the surface.

The Role of Grown-In Defects in Silicon Minority Carrier Lifetime Degradation During Thermal Treatment in Epitaxial Growth Chambers

Severe silicon lifetime degradation was found after its high-temperature treatment in III–V material growth chambers for the fabrication of III–V/Si multijunction solar cells. Further improvement of the cell efficiency requires insights into the root cause of such lifetime degradation and how to protect the silicon lifetime accordingly. While the exact origins of such degradation remain largely unknown, most published work concluded that extrinsic impurities that diffuse into the silicon bulk during the thermal treatment are the sole reason. In this article, we show that while not necessarily present in every float-zone silicon wafer, grown-in defects that can be thermally activated is also a key mechanism behind the observed silicon lifetime degradation during anneal in our molecular beam epitaxy chamber. As such, annealing of the silicon wafer in the furnace at 1000 °C to annihilate the grown-in defects, together with the deposition of a SiNX diffusion barrier to prevent the extrinsic impurities from diffusing into the silicon bulk, are both required to preserve the silicon lifetime throughout the III–V material growth steps.

Epitaxial growth and superconducting properties of thin-film PdFe/VN and VN/PdFe bilayers on MgO(001) substrates.

Single-layer vanadium nitride (VN) and bilayer Pd0.96Fe0.04/VN and VN/Pd0.92Fe0.08 thin-film heterostructures for possible spintronics applications were synthesized on (001)-oriented single-crystalline magnesium oxide (MgO) substrates utilizing a four-chamber ultrahigh vacuum deposition and analysis system. The VN layers were reactively magnetron sputtered from a metallic vanadium target in Ar/N2 plasma, while the Pd1−xFex layers were deposited by co-evaporation of metallic Pd and Fe pellets from calibrated effusion cells in a molecular beam epitaxy chamber. The VN stoichiometry and Pd1−xFex composition were controlled by X-ray photoelectron spectroscopy. In situ low-energy electron diffraction and ex situ X-ray diffraction show that the 30 nm thick single-layer VN as well as the double-layer VN(30 nm)/Pd0.92Fe0.08(12 nm) and Pd0.96Fe0.04(20 nm)/VN(30 nm) structures have grown cube-on-cube epitaxially. Electric resistance measurements demonstrate a metallic-type temperature dependence for the VN film with a small residual resistivity of 9 μΩ·cm at 10 K, indicating high purity and structural quality of the film. The transition to the superconducting state was observed at 7.7 K for the VN film, at 7.2 K for the Pd0.96Fe0.04/VN structure and at 6.1 K for the VN/Pd0.92Fe0.08 structure with the critical temperature decreasing due to the proximity effect. Contrary to expectations, all transitions were very sharp with the width ranging from 25 mK for the VN film to 50 mK for the VN/Pd0.92Fe0.08 structure. We propose epitaxial single-crystalline thin films of VN and heteroepitaxial Pd1−xFex/VN and VN/Pd1−xFex (x ≤ 0.08) structures grown on MgO(001) as the materials of a choice for the improvement of superconducting magnetic random access memory characteristics.

Маска на основе эпитаксиального слоя Si для самокаталитического роста нитевидных нанокристаллов на подложках GaAs (111)B и (100)

GaAs nanowire (NW) self-catalyzed growth on GaAs (111) B and GaAs (100) substrates was carried out by molecular beam epitaxy. A mask for the self-catalyzed NW growth was created by oxidizing an epitaxial silicon layer grown on the GaAs surface by molecular beam epitaxy (MBE). Silicon oxidation was realized in an atmosphere of purified air under normal conditions without moving the structures out from the vacuum system volume of the molecular beam epitaxy chamber. The oxidation process of a silicon layer was studied using single-wave and spectral ellipsometry and the surface morphology of oxidized silicon was studied by atomic force microscopy. Substrates with NWs were studied by scanning electron microscopy. The NW density was demonstrated to be 2.6•107 cm-2 and 3•107 cm-2 for (111)B and (100), respectively.

Defects and the Formation of Impurity ‘Hot Spots’ in HgCdTe/CdZnTe

The formation of impurity ‘hot spot’ macro-defects—localized high impurity level contaminates—is examined. The evolution of macro-defects through their critical stages: as-received CdZnTe substrate, molecular beam epitaxy (MBE) prep etch, Te/oxide desorption and stabilization at deposition temp in MBE chamber, thin (200 nm) HgCdTe deposition, and thick (> 4 μm) MBE HgCdTe deposition, is analyzed. As-received CdZnTe wafers have small and large agglomerations of residual SiO2 and Al2O3 polishing grit. Additionally, macro-defects composed of organic residue, Cd(Zn)Te particulates, and additional impurities are also observed. The MBE preparation etch does not significantly alter the types of defects found on the wafer. The Te/oxide desorption process adds a small number of defects due to colloidal graphite particles. HgCdTe deposition introduces MBE spit defects and Hg droplet residue. There is significant movement of polishing grit and organic macro-defects during the various processing steps. Energy dispersive X-ray spectroscopy (EDS) analysis of MBE spit defects shows they are Cd rich with some of the spit defects containing high concentrations of impurities. The vertical gradient in Te concentration associated with the overgrowth on a metal rich MBE spit defect acts as an impurity pipe for Cu to travel toward the surface to become a ‘hot spot’ defect.

Silicon Nitride Barrier Layers Mitigate Minority-Carrier Lifetime Degradation in Silicon Wafers During Simulated MBE Growth of III–V Layers

We observe a degradation of the minority-carrier lifetime in silicon substrates after a temperature cycle in a molecular beam epitaxy (MBE) chamber that is representative of the growth of III–V materials. This decrease in the lifetime is from milliseconds to microseconds, and in some cases into the sub-microsecond range. The degradation appears to be caused by thermally activated diffusion of metals from the back side of the substrate, occurring at temperatures above 500 °C. This impacts the ability to achieve high-performance monolithic III–V/Si multi-junction solar cells, since the epitaxial growth usually requires high-temperature steps (over 700 °C) for surface de-oxidation or surface reconstruction and temperatures of 400–600 °C during the epitaxial growth. We show that, through phosphorous diffusion gettering, the lifetimes of degraded wafers can be recovered to the millisecond range. Further, we demonstrate that a silicon nitride coating functions both as a diffusion barrier and as an interfacial gettering or hydrogenation agent, enabling high minority-carrier lifetimes directly out of the MBE chamber. This approach allows for the silicon minority-carrier lifetime to be maintained in the millisecond range without the need for post-growth recovery, providing a path to achieve high-efficiency III–V/Si solar cells.

Contact angle stability of gold droplets on top of GaAs nanowires in the non-stationary case

A kinetic model for contact angle stability is introduced for the non-stationary case with time-dependent fluxes in a molecular-beam epitaxy chamber. We present numerical simulations for different regimes of the nanowire growth process.

Molecular beam epitaxy, atomic layer deposition, and multiple functions connected via ultra-high vacuum

Molecular beam epitaxy (MBE) invented for the growth of compound semiconductors in the 70’s has been successfully extended to the advanced growth of metals, oxides, oxide/semiconductor interfaces and emergent topological materials by our endeavor in the past three and half decades. In the 80’s, Kwo et al. have invented metal MBE and oxide MBE methods in pioneering spintronics and high-temperature superconducting oxide films. In driving compound semiconductors for optoelectronics, Hong et al. have produced distributed Bragg reflectors with a continuously graded composition between each constituent without shutter operation, and greatly reduced the electrical resistance; this simple method has made easy manufacture of vertical-cavity surface-emitting lasers. In the 90’s, combining (In)GaAs and oxide MBE chambers via ultra-high vacuum, Hong et al. were the first to unpin the Fermi level in oxide/GaAs, which led to the first demonstration of inversion-channel (In)GaAs metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs). Integrating MBE, atomic layer deposition (ALD), and many other functions in ultra-high vacuum, advances have been made in pushing ultimate complementary MOS (CMOS) of record-high device performances and beyond in growing emergent topological materials for spintronics. Our novel method in preserving as-grown (In)GaAs surfaces and interfaces with high-κ oxides and metals enables employing in-situ synchrotron radiation photoemission to study electronic structures in an atomic scale.

Ultrathin films of L1-MnAl on GaAs (001): A hard magnetic MnAl layer onto a soft Mn-Ga-As-Al interface

Ferromagnetic MnAl (L10-MnAl phase) ultrathin films with thickness varying from 1 to 5 nm have been epitaxially grown on a GaAs (001) substrate. A coercivity above 8 kOe has been obtained with no need of a buffer layer by tuning the sample preparation and the growth parameters. Surface and interface analysis carried out by in situ characterization techniques (x-ray photoelectron spectroscopy and low energy electron diffraction), available in the molecular beam epitaxy chamber, has shown the formation of a ferromagnetic interface consisting of Mn-Ga-As-Al, which contribution competes with the MnAl alloyed film. The appearance of this interface provides important information to understand the growth mechanism of MnAl-based films reported in the literature.

Intentional polarity conversion of AlN epitaxial layers by oxygen

Nitride materials (AlN, GaN, InN and their alloys) are commonly used in optoelectronics, high-power and high-frequency electronics. Polarity is the essential characteristic of these materials: when grown along c-direction, the films may exhibit either N- or metal-polar surface, which strongly influences their physical properties. The possibility to manipulate the polarity during growth allows to establish unique polarity in nitride thin films and nanowires for existing applications but also opens up new opportunities for device applications, e.g., in non-linear optics. In this work, we show that the polarity of an AlN film can intentionally be inverted by applying an oxygen plasma. We anneal an initially mixed-polar AlN film, grown on sapphire substrate by metal-organic vapor phase epitaxy (MOVPE), with an oxygen plasma in a molecular beam epitaxy (MBE) chamber; then, back in MOVPE, we deposit a 200 nm thick AlN film on top of the oxygen-treated surface. Analysis by high-resolution probe-corrected scanning transmission electron microscopy (STEM) imaging and electron energy-loss spectroscopy (EELS) evidences a switch of the N-polar domains to metal polarity. The polarity inversion is mediated through the formation of a thin AlxOyNz layer on the surface of the initial mixed polar film, induced by the oxygen annealing.

Metal work function engineering on epitaxial (100)Ge and (110)Ge metal-oxide-semiconductor devices

Capacitance-voltage characterization of epitaxial n-type (100)Ge and (110)Ge metal-oxide-semiconductor capacitors (MOSCs) was performed using two work function Al and Pt gate metals to evaluate the orientation effect on flat-band voltage (VFB) shift, Fermi level pinning factor (S), and interface induced defects (Dit). These epitaxial (100)Ge/AlAs/GaAs and (110)Ge/AlAs/GaAs heterostructures were grown in-situ using two separate molecular beam epitaxy (MBE) chambers. A VFB shift of >700 mV, S > 0.5, and Dit value of ~ 6 × 1011 cm−2 eV−1 in the energy range of 0.05 eV to 0.3 eV below the conduction band, have been demonstrated from epitaxial n-type (100)Ge and (110)Ge surfaces, which are comparable to the reported bulk Ge MOS-C values, suggesting a robust MOS-C developed process as well as device quality epitaxial (100)Ge and (110)Ge layers on GaAs substrates using an AlAs intermediate buffer. Thus, the metal work function engineering on device-quality MBE grown crystallographically oriented Ge materials, can offer a promising path for extending the performance and application of Ge-based field-effect transistors for low-power devices.

The Growth of GeSn Layer on Patterned Si Substrate by MBE Method

A method to grow high quality GeSn alloy strips with assistance of Sn has been developed, and strips grow laterally on Si(111) substrates in molecular beam epitaxy (MBE) chamber. The GeSn heteroepitaxial strip has been proven to be of good crystalline quality without threading dislocations (TDs) by transmission electron microscopy (TEM). In the meantime, introduction of Sn into Ge was investigated by Raman spectra and energy-dispersive X-ray spectroscopy (EDS). In addition, size and density of GeSn strip can be adjusted by changing the growth conditions, and Sn concentration varies approximately linearly against the epitaxial temperature. Moreover, the Hall mobility of GeSn alloy strips at room temperature was 336 cm2·V-1·s-1 and the carrier concentration was 7.9×1012 cm−3 by Hall measurement. Therefore, the proposed method provides an easy technique to grow high quality GeSn materials for Si-based photonics and microelectronics applications

Reduced recombination in a surface-sulfurized Cu(InGa)Se2 thin-film solar cell

This study demonstrates surface sulfurization effects on Cu(InGa)Se2 (CIGSe) thin-film solar cells with a single back-graded band gap. Single back-graded CIGSe thin films were prepared via a three-stage process in a high-vacuum molecular beam epitaxial growth chamber and were subsequently annealed in a tube furnace under environmental conditions with H2S gas. After sulfurization, an ∼80- to ∼100-nm-thick CuIn(SSe)2 layer with significantly small Ga contents (CISSe:Ga) was formed on the CIGSe layer. The newly formed CISSe:Ga layer exhibited graded S contents from surface to bulk, thus resulting in a front-graded band gap. In addition, CISSe:Ga was covered with S-enriched CISSe region that was extended from the surface to a depth of a few nm and was depleted of Ga. A device with the sulfurized CIGSe showed reduced recombination at the buffer–absorber interface, in space-charge region and in bulk. Consequently, the open circuit voltage increased from 0.58 V (in the non-sulfurized case) to 0.66 V, and the conversion efficiency improved from 15.5 to 19.4%. This large improvement is caused by the front graded band gap at the surface and the hole-blocking barrier, which suppress recombination at the CdS/CISSe:Ga interface. In addition, sulfurization followed by KF post-deposition treatment (PDT) increased the efficiency to 20.1%. Compared to the untreated sulfurized device, the KF-PDT device delivered an increased carrier lifetime and reduced the recombination in bulk probably because the defects were passivated by the K, which penetrated into the bulk region.

Development of a hybrid molecular beam epitaxy deposition system for in situ surface x-ray studies.

A portable metalorganic gas delivery system designed and constructed to interface with an existing molecular beam epitaxy chamber at beamline 33-ID-E of the Advanced Photon Source is described. This system offers the ability to perform in situ X-ray measurements of complex oxide growth via hybrid molecular beam epitaxy. The performance of the hybrid molecular beam epitaxy system while delivering metalorganic source materials is described. The high-energy X-ray scattering capabilities of the hybrid molecular beam epitaxy system are demonstrated both on oxide films grown solely from the metalorganic source and ABO3 oxide perovskites containing elements from both the metalorganic source and a traditional effusion cell.