Modular Reduction Algorithm Research Articles

Software Implementation of Modular Reduction by Pseudo-mersenne Primes

Modern cryptosystems allow the use of operation in prime fields with special kind of modules that can speed up the prime field operation: multiplication, squaring, exponentiation. The authors took into account in the optimizations: the CPU architecture and the multiplicity of the degree of the modulus in relation to the machine word width. As example, shown adopted module reduction algorithms hard-coded for modern CPU in special form of pseudo-Mersenne prime used in MAC algorithm Poly1305, - in electronic signature algorithm EdDSA and - in short message encryption algorithm DSTU 9041. These algorithms have been software implemented on both 32-bit and 64-bit platforms and compared with Barrett modular reduction algorithm for different pseudo-Mersenne and generalized-Mersenne modules. Timings for proposed and Barrett algorithms for different modules are presented and discussed.

Generating Very Large RNS Bases

Residue Number Systems (RNS) are proven to be effective in speeding up computations involving additions and products. For these representations, there exists efficient modular reduction algorithms that can be used in the context of arithmetic over finite fields or modulo large numbers, especially when used in the context of cryptographic engineering. Their independence allows random draws of bases, which also makes it possible to protect against side-channel attacks, or even to detect them using redundancy. These systems are easily scalable, however the existence of large bases for some specific uses remains a difficult question. In this article, we present four techniques to extract RNS bases from specific sets of integers, giving better performance and flexibility to previous works in the litterature. While our techniques do not allow to solve efficiently every possible case, we provide techniques to provably and efficiently find the largest possible available RNS bases in several cases, improving the state-of-the-art on various works of the recent literature.

An Efficient Implementation of KYBER

Quantum algorithms pose a huge threat to the current cryptosystems. In this article, we present a hardware implementation of CRYSTALS-KYBER which is one of the post-quantum cryptosystems based on the Module-LWE problem. Using the proposed modular reduction algorithm, modified modular adder and the reconfigurable data path, the design shares the computing resource for different polynomial related operations, and achieves higher degree of parallelism. Our design is implemented on a Xilinx Artix-7 FPGA. Compared with the leading hardware implementations, our design is more compact, the execution time is shorter, and it significantly consumes fewer registers.

Reliability evaluation of all-user terminals in LEO satellite communication network based on modular reduction

LEO satellite communication network has a large number of satellites distributed in low orbits, which leads to multiple coverage of many areas on the ground. It is hard work to describe and evaluate the reliability of LEO satellite communication network. To solve this problem, the reliability of all-user terminals in LEO satellite communication network is defined, and the corresponding reliability evaluation method is proposed in the paper. Due to the large scale of the interstellar network, a modular reduction algorithm using the modular network instead of the original network for state decomposition is proposed in this paper. Case study shows that the calculation time of the proposed method is equivalent to 6.28% of the original state space decomposition algorithm. On this basis, the reliability of LEO satellite communication network is further analyzed. It is found that the reliability of LEO satellite network was more sensitive to the reliability of Inter-Satellite link and the satisfaction of global coverage in the early stage, and it is more sensitive to the reliability of the satellite in the later stage. The satellite-ground link has a relatively constant impact on of LEO satellite network.

Montgomery-friendly primes and applications to cryptography

This paper deals with Montgomery-friendly primes designed for the modular reduction algorithm of Montgomery. These numbers are scattered in the literature and their properties are partially exploited. We exhibit a large family of Montgomery-friendly primes which give rise to efficient modular reduction algorithms. We develop two main outcomes. The first one is dedicated directly to cryptography, in particular for isogeny-based approaches and more generally to elliptic curves cryptography (ECC). We suggest more appropriate finite fields and curves in terms of complexity for the recommended security levels, for both isogeny-based cryptography and ECC. The second issue is mainly arithmetic (even if its main use is cryptography), and we propose families of alternative RNS bases. We show that, for dedicated architectures with word operators, we can reach, for a same or better complexity, larger RNS bases with Montgomery-friendly pairwise co-primes than the RNS bases generally used in the literature with pseudo-Mersenne numbers.

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation

In the SIKE implementation, the Montgomery representation has been mostly adopted in the finite field arithmetic computing as the corresponding reduction algorithm is considered the fastest method for implementing the modular reduction. In this paper, we propose a new data representation for the supersingular isogeny-based elliptic-curve cryptography (ECC), of which the SIKE is a subclass. The new representation can facilitate faster modular reduction implementation than the Montgomery reduction. Meanwhile, the other finite field arithmetic operations in the ECC can also benefit from the proposed data representation. We have implemented all the arithmetic operations in C language with constant execution time based on our proposed data representation and applied them to the newest SIKE software library. Targeting at the SIKEp751, we run our design and the optimized generic implementation on a 2.6GHz Intel Xeon E5-2690 processor. The experiment results show that for the parameters of SIKEp751, the proposed modular reduction algorithm is about 2.61x faster than the best Montgomery one and our scheme also performs significantly better for the other finite field operations. With these improvements, the overall software implementation for the SIKEp751 achieves about 1.65x speedup compared to the state-of-the-art generic implementatio

A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

Implementation of RSA Signatures on GPU and CPU Architectures

This paper reports a constant-time CPU and GPU software implementation of the RSA exponentiation by using algorithms that offer a first-line defense against timing and cache attacks. In the case of GPU platforms the modular arithmetic layer was implemented using the Residue Number System (RNS) representation. We also present a CPU implementation of an RNS-based arithmetic that takes advantage of the parallelism provided by the Advanced Vector Extensions 2 (AVX2) instructions. Moreover, we carefully analyze the performance of two popular RNS modular reduction algorithms when implemented on many- and multi-core platforms. In the case of CPU platforms we also report that a combination of the schoolbook and Karatsuba algorithms for integer multiplication along with Montgomery reduction, yields our fastest modular multiplication procedure. In comparison with previous literature, our software library achieves faster timings for the computation of the RSA exponentiation using 1024-, 2048- and 3072-bit private keys.

An improvement of the Barrett modular reduction algorithm

The popular Barrett modular reduction algorithm requires a suitably chosen base b≥3. In this paper, we show that the setting will cause the problem of data expansion and require more cost for performing the unique multiplication which dominates the cost of this algorithm. We shall prove that the base b can be replaced by the usual base 2. The improvement gives a little of cost saving. Besides, it is more portable and more suitable for small devices such as smartphones.

Efficient and formally proven reduction of large integers by small moduli

On w -bit processors which are much faster at multiplying two w -bit integers than at dividing 2 w -bit integers by w -bit integers, reductions of large integers by moduli M smaller than 2 w -1 are often implemented suboptimally, leading applications to take excessive processing time. We present a modular reduction algorithm implementing division by a modulus through multiplication by a reciprocal of that modulus, a well-known method for moduli larger than 2 w -1 . We show that application of this method to smaller moduli makes it possible to express certain modular sums and differences without having to compensate for word overflows. By embedding the algorithm in a loop and applying a few transformations to the loop, we obtain an algorithm for reduction of large integers by moduli up to 2 w -1 . Implementations of this algorithm can run considerably faster than implementations of similar algorithms that allow for moduli up to 2 w . This is substantiated by measurements on processors with relatively fast multiplication instructions. It is notoriously hard to specify efficient mathematical algorithms on the level of abstract machine instructions in an error-free manner. In order to eliminate the chance of errors as much as possible, we have created formal correctness proofs of our algorithms, checked by a mechanized proof assistant.

Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed–Solomon Codec

In this paper, we present efficient algorithms for modular reduction to derive novel systolic and non-systolic architectures for polynomial basis finite field multipliers over GF(2m) to be used in Reed-Solomon (RS) codec. Using the proposed algorithm for unit degree reduction and optimization of implementation of the logic functions in the processing elements (PEs), we have derived an efficient bit-parallel systolic design for finite field multiplier which involves nearly two-thirds of the area-complexity of the existing design having the same time-complexity. The proposed modular reduction algorithms are also used to derive efficient non-systolic serial/parallel designs of field multipliers over GF(28) with different digit-sizes, where the critical path and the hardware-complexity are further reduced by optimizing the implementation of modular reduction operations and finite field accumulations. The proposed bit-serial design involves nearly 55% of the minimum of area, and half the minimum of area-time complexity of the existing bit-serial designs. Similarly, the proposed digit-serial/parallel designs involve significantly less area, and less area-time complexities compared with the existing designs of the same digit-size. By parallel modular reduction through multiple degrees followed by appropriate logic-level sub-expression sharing; a hardware-efficient regular and modular form of a balanced-tree bit-parallel non-systolic multiplier is also derived. The proposed bit-parallel non-systolic pipelined design involves less than 65% of the area and nearly two-thirds of the area-time complexity of the existing bit-parallel design for a RS codec, while the non-pipelined form offers nearly 25% saving of area with less time-complexity.

Fast algorithm for modular reduction

The paper presents an algorithm for computing the residue R = X mod M. The algorithm is based on a sign estimation technique that estimates the sign of a number represented by a carry-sum pair produced by a carry save adder. Given the (n + k)-bit X and the n-bit M, the modular reduction algorithm computes the n-bit residue R in O(k + log n) time, and is particularly useful when the operand size is large. We also present a variant of the algorithm that performs modular multiplication by interleaving the shift-and-add and the modular reduction steps. The modular multiplication algorithm can be used to obtain efficient VLSI implementations of exponentiation cryptosystems.