Modified Signed-digit Research Articles

Research on Multiplication Routine Based on Reconfigurable Four-Valued Logic Processor

Despite the indispensable role of traditional electronic computers in modern society, their limitations in parallel processing capabilities, bit-width constraints, and processor bit-width are becoming increasingly apparent, especially when handling large-scale datasets and complex computational tasks. Although hardware technology and algorithm optimization continue to advance, the arithmetic units of traditional computers—adders—remain constrained by carry delay and bit-width limitations. This bottleneck is particularly pronounced in multiplication operations, mainly when adders are used for partial product accumulation. However, since 2018, the emergence of a new type of Reconfigurable Four-Valued Logic Electronic Processor (RFLEP) has provided a potential solution to these traditional limitations. With its large processor bit-width, flexible bit grouping capabilities, and dynamic hardware function reconfiguration features, this processor has brought revolutionary changes to the field of computing. In this context, this paper proposes and implements a Reconfigurable Four-Valued Logic Multiplication Routine (RFLMR) tailored explicitly for the RFLEP. The RFLMR utilizes the Modified Signed-Digit (MSD) representation method in multi-valued logic combined with the M transformation in four-valued logic to generate partial products. These partial products are then efficiently summed in parallel using the JW-MSD parallel adder, achieving the rapid execution of multiplication operations. Experimental results demonstrate that the multiplication routine based on the RFLEP performs multiplication operations accurately and meets theoretical expectations regarding implementation efficiency and performance. This research not only provides new ideas for developing next-generation high-performance computing systems but also paves the way for exploring more efficient and powerful computing models, heralding a profound transformation in future computing technology.

Design and implementation of the Walsh-Hadamard transform on a ternary optical computer.

Walsh-Hadamard is a commonly used mathematical transformation, a mathematical method for spectrum analysis in the real number domain, which has been widely used in many fields such as digital signal processing, spectral modulation, and image processing. Based on the characteristics of the ternary optical computer with a large number of processor bits, reconfigurable bit functions, and parallel computation, a ternary optical processor with all bits allocated is given, and the transformations T,W,T',W',T2 of modified signed-digit (MSD) addition are reconfigured. On this basis, by configuring AdderN MSD adders on the optical processor, the N-point Walsh-Hadamard transform fast parallel computing approach is given. It requires only 3×⌊N/AdderN⌋ clock cycles to compute the Walsh-Hadamard transform of N points under parallel computing. Furthermore, complexity analysis shows that the clock cycles in an electronic computer are N/3 times that of in a ternary optical computer under the fully parallel optical computation. The experiment of the Walsh-Hadamard transform with eight points shows that parallel optical computing has more advantages than the conventional electronic computer in fast computing the problems with characteristics of parallel computing. At the same time, it highlights the advantages and potential of ternary optical computers in data-intensive computing.

Design and implementation of bitwise parallel MSD square rooting in ternary optical computer

The square rooting is one of the most important basic operations in computers. Researchers have been studying its algorithms and obtained many algorithm implementations. But improving the accuracy and speed of the square rooting has always been a problem of great concern in electronic computers, embedded systems, and other new computing systems. Based on the parallel carry-free modified signed digit (MSD) adder, the bitwise square rooting of MSD numbers and the floating numbers are proposed in this paper. The parallel square rooting for single MSD integers and multiple MSD integers are presented on a ternary optical computer (TOC) processor. The clock cycles required for the square rooting of multiple groups of MSDs of equal length are the same with that of the single MSD data, which is ( 3 + log ( ⌈ n / 2 ⌉ ) ) ⌈ n / 2 ⌉ for n-bit MSD integer requires. It is proved that the square rooting for any MSD form and for the binary form of a decimal number may differ only at the lowest digit in their final binary square rooting representations. As an experiment, the square rooting is designed and implemented on a 192-bit prototype SD16 of TOC. Theoretical proof and optical experiments show that the bitwise MSD square rooting is feasible and can greatly improve the efficiency of square rooting for big data. It makes full use of the advantages of the ternary optical processor with a large number of digits, reconfigurable computing functions, and bitwise allocation.

Research on fully parallel matrix algorithm of ternary optical computer for the shortest path problem.

The shortest path is an extensive algorithm problem in graph theory. When faced with a huge amount of data in the shortest path problem, the problem with using traditional algorithms is the slow operation speed and high power consumption. To address these problems, this paper proposes a fully parallel matrix (FPM) algorithm. It uses the matrix multiplication principle and one-step modified signed-digit (MSD) adder, which can effectively implement parallel computing in ternary optical computers (TOCs). Finally, we compare clock cycles, and the results show that the TOC-based FPM algorithm can efficiently reduce the calculation time when solving the shortest path problem.

Ternary logical naming convention and application in ternary optical computers

This article introduces the ternary logical naming convention, which was newly discovered in the study of logical units of ternary optical computers (TOCs). First, the design principle and design specification of the ternary logical naming convention are elaborated in detail and several examples are given to illustrate the use of the naming convention. Second, taking the modified signed-digit (MSD) adder of the TOC as an example, the naming convention is applied to build four ternary logical units of the MSD adder, and the implementation method of pipelined addition is introduced. Finally, the correctness of the ternary logical naming convention proposed in this paper and the usability of the adder built according to this convention are illustrated by experiments. The ternary logical naming convention can easily obtain the relationship between the ternary logic transforms, thus judging the characteristics of the logic units of TOCs, which is helpful to promote the in-depth study of TOCs in the field of numerical calculation.

The application of SJ-MSD adder to mean value filtering processing

Based on the transformations of SJ-MSD (modified-signed digit) addition and the principle of SJ-MSD adder, the application of SJ-MSD adder of TOC to mean value filtering (ternary optical computer) is introduced. The realization of mean filtering processing is presented by reconfiguring SJ-MSD adders on TOP (ternary optical processor) in detail. Experiments show that the mean filter processing in TOC can be carried out successfully with a multiple of SJ-MSD parallel adders with large number of data bits. It also shows a great promise and advantages for the application of TOC in digital image processing and other respects.

Optical computer based application platform for MSD multiplication

As one of the most commonly used operations, multiplication has been widely used as the basis of other numerical operations. In order to simplify the multiplication application on Ternary Optical Computer (TOC), the mechanisms about the implementation of carry-free multiplication on TOC are discussed. And a modified signed-digit (MSD) based multiplication platform is designed and implemented. Using the platform, users only need to input the necessary operation parameters without needing to know any details about TOC. The platform automatically generates the necessary information that is needed in multiplication according to the application requests. And it sends the information formatted to the slave computer of TOC which answers for monitoring and controlling the operation process. Meanwhile, it answers for sending back the results to the users when the operation is accomplished. Experimental results show the multiplication application platform is feasible and correct. It can much simplify the multiplication application on TOC and can be used as the basis of other kinds of applications.

Design of MSD multiplier for ternary optical computer processor based on minimum module

In view of the inefficiency of multi-digit multiplication in the current Ternary Optical Computer (TOC), it is difficult to achieve fast multiplication. Based on the one-step MSD (Modified Signed-Digit) adder, M operator, MSD multiplication principle and divide and conquer strategy, the 4-bit minimum module is designed and implemented, which can perform 4-bit multiplication. Besides, multiple minimum modules can perform operations in parallel. Based on which, the expansion scheme is proposed to achieve fast multiplication without digit limitation. This paper elaborates on the design principle, operation steps, optical path structure and expansion scheme of the 4-bit minimum module. The MSD multiplier based on the minimum module (MMM) is compared with the existing optical multiplier and the multiplier of electronic computer in the same type in terms of computational time complexity. The results show that the MMM is better than the other multipliers in the processing of multi-digit multiplication. It can give full play to the main advantages of TOC, which are giant data-bits parallel computing and reconfigurable processor, and it has more practical application significance.

A Carry-Free Multiplication Implementation Method

Delay caused by carry propagation is an unfavourable issue that much affects the efficiency of numerical computing in computer system. And the more data bits of the operands, the worse the delay. As data bits of the operands in optical computer can be huge because of the high information capability of light, this makes carry delay be very serious. As multiplication is one of the most important and popular calculations and many multiplications can be carried out in parallel by utilizing huge number of data bits of optical computer, study on how to reduce or even mitigate carry delay in multiplication is very important. To improve the multiplication efficiency, a new carry free method to design and implement multiplication based on Ternary Optical Computer (TOC) is put forward. Fully considering the relations between the operands based on modified signed-digit (MSD) number system, a parallel mulitplication implemeation strategy together with its resource allocation method is presented. The experimental results show that the proposed strategy is correct. It exerts the advantages of optical computing and ensures that no carry delay is introduced in the process of multiplication which much improves the efficiency of optical multiplication applications.

Carry-free full-symbol one-step modified signed-digit addition.

Optical computing has advantages over electronic computing because it can carry much more information and process more data bits. Providing that carry-look-ahead is applied in optical computing in the same way electronic computing accomplishes addition calculation, it will be more inefficient because of the delay caused by a large number of serial carries. On the basis of the research on relations among the augend, addend, results, and the redundancy of modified signed-digit (MSD) number, the implementation method of carry-free one-step MSD addition is presented. Meanwhile, the corresponding logical light path scheme is designed in this paper. Extensive experimental results show that the proposed implementation method of one-step addition is correct, and the designed light path scheme is reasonable.

An optical implementation method for symmetric MSD number

Symmetric modified signed-digit (MSD) number is much advantageous over other numbers. It can implement optical addition operation in one step without carry delay which will much affect the efficiency of numerical operation in computer system. However, study on how to obtain symmetric MSD (SMSD) number has been little concerned. Based on the mapping relations between common MSD number and SMSD number, conversion rules are presented. Following the rules, the optical paths of the converters to implement the conversion are designed. Combining the converters, the optical path of the general converter that can be used to implement the conversion from common MSD number to SMSD number is presented. Simulation results show that the method and the optical path of the converter are correct. They can be used to effectively convert MSD number into the corresponding SMSD number.

Design and implementation of the modified signed digit multiplication routine on a ternary optical computer.

Multiplication with traditional electronic computers is faced with a low calculating accuracy and a long computation time delay. To overcome these problems, the modified signed digit (MSD) multiplication routine is established based on the MSD system and the carry-free adder. Also, its parallel algorithm and optimization techniques are studied in detail. With the help of a ternary optical computer's characteristics, the structured data processor is designed especially for the multiplication routine. Several ternary optical operators are constructed to perform M transformations and summations in parallel, which has accelerated the iterative process of multiplication. In particular, the routine allocates data bits of the ternary optical processor based on digits of multiplication input, so the accuracy of the calculation results can always satisfy the users. Finally, the routine is verified by simulation experiments, and the results are in full compliance with the expectations. Compared with an electronic computer, the MSD multiplication routine is not only good at dealing with large-value data and high-precision arithmetic, but also maintains lower power consumption and fewer calculating delays.

The symmetric MSD encoder for one-step adder of ternary optical computer

The symmetric Modified Signed-Digit (MSD) encoding is important for achieving the one-step MSD adder of Ternary Optical Computer (TOC). The paper described the symmetric MSD encoding algorithm in detail, and developed its truth table which has nine rows and nine columns. According to the truth table, the state table was developed, and the optical-path structure and circuit-implementation scheme of the symmetric MSD encoder (SME) for one-step adder of TOC were proposed. Finally, a series of experiments were designed and performed. The observed results of the experiments showed that the scheme to implement SME was correct, feasible and efficient.

Design of a high-efficient MSD adder

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

Signed digit data hiding scheme

The EMD (Exploiting Modification Direction) method by Zhang and Wang uses (2n+1)-ary notation to achieve secret message embedding into a cover image. However, the maximum capacity of this method is 1.16 bpp for cover pixel number n=2. Its embedding capacity rapidly decreases when selected pixels increase. In order to improve this shortcoming, a new data hiding scheme based on MSD (Modified Signed-Digit) is proposed. There are three major contributions in this proposed scheme. The first is only ⌈n2⌉ pixels will be modified and the value is +1 or −1 when the group has n pixels. Secondly, the embedded capacity maintains at least 1 bpp when n is increasing. The last is the stego image quality is better than 52 dB when the cover image's pixels are greater than 4 for each group.

Design and Implementation of Modified Signed-Digit Adder

How to fully apply the characteristics and advantages of light in numerical computation is an important issue that attracts many scholars. Though much research has been done in this field, how to design and realize specific applications or devices is still an issue to be solved. Based on this, we present an architecture and implementation method of modified signed-digit (MSD) optical adder from the point of applicability. In the implementation, we fully consider the different procedures of the MSD addition which including optical logical operation, results decoding, special storage area design, data feedback, control of light path, etc. Meanwhile, we also introduce pipeline mechanism which guarantees that the addition operation is an automatic and continuous process. This is a carry free adder design method which guarantees the addition has high data throughput. It is very suitable to fulfill the large-scale numerical computation. The experiment shows, the MSD adder not only has a reasonable and correct design, but also has high throughput rate, can work efficiently and steadily.

Ultra-fast all-optical polarization-encoded modified signed-digit addition using terahertz-optical-asymmetric-demultiplexer (TOAD) switches

In this paper, enhanced designs for ultra-fast all-optical circuits based on the terahertz-optical-asymmetric-demultiplexer (TOAD) adders are proposed. The high speed is achieved due to the use of the nonlinear optical materials and the nonbinary modified signed-digit (MSD) number representation. The proposed all-optical circuits use polarized light to present the trinary digits of the MSD numbers. It will be shown that the polarization-encoded MSD adder uses much less TOADs switches (37.5% less) and it is faster by 33.33% compared to the intensity-encoded ones.

Design and implementation of the one-step MSD adder of optical computer

On the basis of the symmetric encoding algorithm for the modified signed-digit (MSD), a 7*7 truth table that can be realized with optical methods was developed. And based on the truth table, the optical path structures and circuit implementations of the one-step MSD adder of ternary optical computer (TOC) were designed. Experiments show that the scheme is correct, feasible, and efficient.

Principle of MSD floating-point division based on Newton-Raphson method on ternary optical computer

The division operation is not frequent relatively in traditional applications, but it is increasingly indispensable and important in many modern applications. In this paper, the implementation of modified signed-digit (MSD) floating-point division using Newton-Raphson method on the system of ternary optical computer (TOC) is studied. Since the addition of MSD floating-point is carry-free and the digit width of the system of TOC is large, it is easy to deal with the enough wide data and transform the division operation into multiplication and addition operations. And using data scan and truncation the problem of digits expansion is effectively solved in the range of error limit. The division gets the good results and the efficiency is high. The instance of MSD floating-point division shows that the method is feasible.

Principles and construction of MSD adder in ternary optical computer

The two remarkable features of ternary values and a massive unit with thousands bits of parallel computation will make the ternary optical computer (TOC) with modified signed-digit (MSD) adder more powerful and efficient than ever before for numerical calculations. Based on the decrease-radix design presented previously, a TOC can satisfy either a user requiring huge capacity for data calculations or one with a moderate amount of data, if it is equipped with a prepared adder. Furthermore, with the application of pipelined operations and the proposed data editing technique, the efficiency of the prepared adder can be greatly improved, so that each calculated result can be obtained almost within one clock cycle. It is hopeful that by employing a MSD adder, users will be able to enter a new dimension with the creation of a new multiplier, new divider, as well as new matrix operator in a TOC in the near future.