Design and implementation of bitwise parallel MSD square rooting in ternary optical computer

Abstract

The square rooting is one of the most important basic operations in computers. Researchers have been studying its algorithms and obtained many algorithm implementations. But improving the accuracy and speed of the square rooting has always been a problem of great concern in electronic computers, embedded systems, and other new computing systems. Based on the parallel carry-free modified signed digit (MSD) adder, the bitwise square rooting of MSD numbers and the floating numbers are proposed in this paper. The parallel square rooting for single MSD integers and multiple MSD integers are presented on a ternary optical computer (TOC) processor. The clock cycles required for the square rooting of multiple groups of MSDs of equal length are the same with that of the single MSD data, which is ( 3 + log ( ⌈ n / 2 ⌉ ) ) ⌈ n / 2 ⌉ for n-bit MSD integer requires. It is proved that the square rooting for any MSD form and for the binary form of a decimal number may differ only at the lowest digit in their final binary square rooting representations. As an experiment, the square rooting is designed and implemented on a 192-bit prototype SD16 of TOC. Theoretical proof and optical experiments show that the bitwise MSD square rooting is feasible and can greatly improve the efficiency of square rooting for big data. It makes full use of the advantages of the ternary optical processor with a large number of digits, reconfigurable computing functions, and bitwise allocation.