Modified Gate Diffusion Input Technique Research Articles

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor

For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CMOS logic and a Modified GDI technique. Also, the power dissipation of all these circuits have been calculated and compared for CMOS and Modified GDI. The designing and simulations have been done on Cadence Virtuoso tool in 90 nm technology and power supply voltage has been taken as 1 V.

Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique

In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter.

A Review On Modified Gate Diffusion Input Logic: An Approach For Area And Power Efficient Digital System Design

In recent days, the main motto of VLSI designers is to reduce the power and area as devices are becoming battery-operated, compact and require enhanced functionality and features. Due to the scaling and shrinking of devices, the transistor leakage power has increased at an exponential rate. In this paper, analysis on the research based on the Modified gate diffusion input technique (m-GDI) which has gained much attention in recent days are encompassed. Consequently, 31 research papers homologous to m-GDI technique are assessed and analysed based on the numerous targets. In this review, we present the m-GDI Technique, a low power technique and scrutinize the modern breakthroughs with several pros and cons. The thorough examination is done on finding the inclusion of the issues, methodologies, simulation tools and technologies used.

Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. The primary issues in the design of adder cell are area, delay and power dissipation. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper mainly presents the design of 5 different full adder topologies using Modified Gate Diffusion Input Technique. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. This paper focuses two main design approaches. The former presents the implementation of modified primitive logic cells and its performance issues were compared with GDI and CMOS logic. The latter presents the implementation of 5 different modified GDI full adders and its performance issues. The simulation results reveal better delay and power performance for the proposed modified GDI full adders when compared with the existing GDI technique, CMOS and pass transistor logic at 0.250μm CMOS technologies. Delay and power has been evaluated by Tanner simulator using TSMC BSIM 0.250μm technologies.