Modified Carry Select Adder Research Articles

Vedic Multiplier Design Using Modified Carry Select Adder with Parallel Prefix Adder

Vedic Multiplier Design Using Modified Carry Select Adder with Parallel Prefix Adder

Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture

Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture

Design of Vedic Multiplier Using SQRT Carry Select Adder (CSLA)

Vedic multiplier is designed using area-efficient Carry Select Adder (CSLA). As the multiplication is the process of subsequent addition, adder is important block in implementation of multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead of simple Ripple Carry Adder (RCA). Carry select adder is known to be one of the fastest adder structures. Here Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. The goal is to design Vedic multiplier based on crosswise and vertical algorithms using area efficient Sqrt CSLA. Conventional CSLA designs like Binary to Excess one Converter (BEC) based CSLA and Modified CSLA (MCSLA) are compared with proposed CSLA design to prove its efficiency. It shows improved performance in terms of area. This renovated CSLA is used to design proposed Vedic multiplier. The proposed Sqrt CSLA based Vedic multiplier provides better results in power and speed of the digital circuits.

Energy Efficient BEC Modified Carry Select Adder Based PTMAC Architecture for Biomedical Processors

AbstractPower dissipation is considered as the critical objective in the design of integrated circuits. Concern has increased in the design of adders, which form the basic computational block of any circuit. Research work has been carried out towards the efficient design and performance analysis of Carry Select Adder. Carry Select Adder (CSLA) is used in many data processors to increase the speed of mathematical calculation. The main aim of this paper is to reduce the power by using Binary to Excess-1 Converter, which uses an uncomplicated and proficient gate-level adaptation to reduce the power and area of the Carry Select Adder to a tolerant level. Based on the analysis, the proposed design proves to be better than the Conventional CSLA, BEC Modified Carry Select Adder and the Regular Square Root CSLA. Moreover, the Programmable Truncated Multiplier and Accumulator Circuit architecture designed using the BEC modified CSLA can be used for low power biomedical instrumentation with a need for reticent digi...

Performance Improvement Of A Modified Carry Select Adder

Performance Improvement Of A Modified Carry Select Adder

Low Power, Area-Efficient and High Speed Fast Adder for Processing Element

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate - level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA), Regular Square Root CSLA (SQRT CSLA), Modified SQRT CSLA and Proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSLA.

Low Power 256-bit Modified Carry Select Adder

Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. When compared to earlier Ripple Carry Adder and Carry Look Ahead Adder, Regular CSLA (R-CSLA) is observed to provide optimized results in terms of area. This study proposes an efficient method which replaces the RCA using BEC. The modified CSLA architecture has been developed using gate-level modification to significantly reduce the delay and power of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-bit Square-Root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design for 256-bit has reduced power and delay as compared with the regular SQRT CSLA. Designs were developed using structural Verilog module and synthesized using Xilinx ISE simulator and the implementation is done in cadence RTL compiler using 0.18 μm technology. For 256-bit addition in this study, it is proposed to simple gate level modification which significantly reduces the power by 19.4% when compared with R-CSLA. The result analysis shows that the proposed architecture achieves two folded advantages in terms of delay and power.

Design of Low Power, Area-Efficient Carry Select Adder

Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.