Modified Booth Encoding Research Articles

Design of Efficient Multiply-Accumulate Unit for Convolutional Neural Networks

Convolutional Neural Networks (CNN) are used in a range of machine learning tasks, such as voice, image, and video processing. As the demand for faster response times in real-time applications grows, the need for high-speed implementation of CNNs is becoming more significant. However, the convolutional layer of CNNs is computationally demanding, leading to higher delays. Therefore, this study seeks to design an efficient and fast convolution block for the hardware implementation of the CNN algorithm. The proposed solution uses a Bit-Level Multiplier and Accumulator (BLMAC) unit that incorporates a modified Booth Encoder and Wallace Reduction Tree to achieve time optimization. The BLMAC, a key component of the convolution process, is optimized for speed. The area occupied by this architecture is 2761.517μm2, the power consumed is 121.4μW, and the delay is 9.11ns. Hence the proposed architecture is extremely power efficient and other parameters like area and delay have not been sacrificed to achieve this result. The proposed BLMAC architecture is designed using Verilog. The testbench for the code was verified and simulated in Cadence NCSIM. The synthesis is done in the Genus tool offered by Cadence.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier

Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and designed for the reduction of power in partial product reduction

Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology

Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier

ABSTRACT Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction.

Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design

Convolutional Neural Network (CNN) plays an important role in several machine learning tasks related to speech, image, and video processing applications. The increasing demand for faster processing in real-time applications requires high-speed implementation of CNN. However, in general, CNN involves higher latency due to the computationally intensive behavior of the convolutional layer. While state-of-the-art architecture provides efficient dataflow of the convolutional operations, this paper proposes a hardware-efficient, high-speed convolution block for ASIC implementation of the CNN algorithm. The proposed convolution block is designed using a novel bit-level-multiply-accumulator (BLMAC) with a modified Booth encoder and a Wallace reduction tree. The critical path of the overall architecture is significantly shortened due to the time-optimized implementation of the proposed BLMAC, which is a main component of the convolution process. Critical path analysis and dataflow strategy are also provided to demonstrate the acceleration of the proposed design. The proposed architecture was synthesized using Synopsys Design Compiler to prove its accelerated processing. The ASIC synthesis results of the proposed architecture using a 65nm standard cell library show at least 53% reduction in latency, 52.2% reduction in area-delay product, and 54.2% reduction in power-delay product compared to the state-of-the-art architecture.

Implementation of efficient MAC for DSP applications using Modified Booth Encoding algorithm technique

Multiplier and MAC is fundamental elements in DSP processors. Multiplication is one of the essential functions of arithmetic operation in computing systems, performing with different multipliers with different algorithms. MAC consisting of multiplier, adder and accumulator which plays a vital role in various DSP applications in improving signal processing ability, FIR and IIR filters. This article concentrates particularly on the efficient implementations of an accurate, signed and unsigned point multiplier. A modified booth Encoding (MBE) multiplier is used to execute a multiplier in floating point multiplier in order to significantly reduce partial products into half. CSA is applied with the inclusion of partial products in order into half. CSA is applied with the inclusion of partial products in order to improve speed.Rounding is not introduced to make the multiplier of a MAC unit more precise. Hence the proposed system shows an improved performance in systems area by 64.77%, reduced surplus power consumption by 44.41%, delay is reduced by 80% and shows a less circuit cost efficient. This proposed system area, power, delay, area delay product and power delay product are designed and calculated using synopsis, advanced VLSI tool.

Improved Signed Binary Multiplier Through New Partial Product Generation Scheme

In this paper, a novel partial product generation (PPG) scheme has been proposed based on the shift and the add logic of multiplier bits to introduce a radix-4 and radix-16 signed binary multiplications (SBMs). The proposed PPG methodology encodes two bits for radix-4 and four bits for radix-16 at a time, whereas the traditional modified Booth encoding (MBE) for radix-4 and radix-16 encodes three bits and five bits, respectively, at a time, which offers the reduction of the encoder combinations. In the proposed design, the multiplication sign extension is pre-decided from the most significant bit (MSB) of the multiplier and the multiplicand, thereby subtraction operation for multiplication is removed from traditional MBE. The simulation results of the proposed SBMs architecture offer a significant improvement in power, delay and power-delay-product (PDP). The PDP was reduced by [Formula: see text]%, [Formula: see text]% and [Formula: see text]%, respectively, with proposed radix-4 SBM and by [Formula: see text]%, [Formula: see text]% and [Formula: see text]%, respectively, with proposed radix-16 SBM for [Formula: see text]-, and [Formula: see text]-bit multiplication, respectively, when compared with the existing state-of-the-art designs.

WITHDRAWN: Design of multiplier for arithmetic-high-level synthesis using modified booth encoding

Though there are various types of multipliers presently, although fractional multipliers effectively planned through making a few sections working in equal, the structure of halfway convey spare multipliers is additionally testing. Earlier methodologies proposed a few arrangements using booth recoding with radix-4. The present system forms it conceivable to decrease the stature considerably, which is the utmost broad choice while planning, just simple products recommended. Bigger values of radix in addition decreases to the detriment in presence of products. So as to relieve the deferral, from the former studies, initially recommended to detach calculation utilizing the accessible leeway. Normally in binary multiplication and operation is used for partial products of multiplier and multiplicand. In case of Booth Multiplier the multiples are encoded. For n bit by n-bit multiplication, n/2 partial products are obtained for radix 4 and n/3 for radix-8. Thinking about this, encoding method is implemented so that partial products are reduced. In the proposed methodology we will use modified carry skip adder for high speed operation.

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI hierarchical array architecture for balanced (2 n -1, 2 n , 2 n +1) and unbalanced (2 k -1, 2 k , 2 k +1) word-length moduli are proposed which is capable of handling signed input numbers. Balanced 2 n -1 SRM is used as a reference to design an unbalanced 2 k -1 and 2 k +1. The synthesized results show that the proposed 2 n -1 SRM architecture achieves 17% of the area, 26% of speed and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel hierarchical approach adopted for the design which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n -1, 2 n , 2 n +1} special moduli set based RNS processor and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bits, which resulted in a reduction of the power delay product. Approximate computing is a relevant technique for low power and high performance circuits as used in error-tolerant applications. Approximate or inexact computing is an attractive design methodology for low power design but accomplished by loosening up the necessity of precision. It becomes critical to maintain full accuracy to attain reduced power utilization. In this paper, the design of approximate redundant binary (RB) multipliers is studied and modified to build less complex multiplier with Radix-8 modified booth encoding technique to reduce area and complexities of architectures.

Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

Approximate computing is an emerging technique in which power-efficient circuits are designed with reduced complexity in exchange for some loss in accuracy. Such circuits are suitable for applications in which high accuracy is not a strict requirement. Radix-4 modified Booth encoding is a popular multiplication algorithm which reduces the size of the partial product array by half. In this paper, three Approximate Booth Multiplier Models (ABM-M1, ABM-M2, and ABM-M3) are proposed in which approximate computing is applied to the radix-4 modified Booth algorithm. Each of the three designs features a unique approximation technique that involves both reducing the logic complexity of the Booth partial product generator and modifying the method of partial product accumulation. The proposed approximate multipliers are demonstrated to have better performance than existing approximate Booth multipliers in terms of accuracy and power. Compared to the exact Booth multiplier, ABM-M1 achieves up to a 23 percent reduction in area and 15 percent reduction in power with a Mean Relative Error Distance (MRED) value of $7.9\times 10^{-4}$7.9×10-4. ABM-M2 has area and power savings of up to 51 and 46 percent respectively with a MRED of $2.7\times 10^{-2}$2.7×10-2. ABM-M3 has area savings of up to 56 percent and power savings of up to 46 percent with a MRED of $3.4\times 10^{-3}$3.4×10-3. The proposed designs are compared with the state-of-the-art existing multipliers and are found to outperform them in terms of area and power savings while maintaining high accuracy. The performance of the proposed designs are demonstrated using image transformation, matrix multiplication, and Finite Impulse Response (FIR) filtering applications.

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing

Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approximate Booth encoders are proposed and analyzed for error-tolerant computing. The error characteristics are analyzed with respect to the so-called approximation factor that is related to the inexact bit width of the Booth multipliers. Simulation results at 45 nm feature size in CMOS for delay, area and power consumption are also provided. The results show that the proposed 16-bit approximate radix-4 Booth multipliers with approximate factors of 12 and 14 are more accurate than existing approximate Booth multipliers with moderate power consumption. The proposed R4ABM2 multiplier with an approximation factor of 14 is the most efficient design when considering both power-delay product and the error metric NMED. Case studies for image processing show the validity of the proposed approximate radix-4 Booth multipliers.

EFFICIENT FLOATING POINT FAST FOURIER TRANSFORM BUTTERFLY ARCHITECTURE USING BINARY SIGNED DIGIT MULTIPLIER AND ADDERS

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease.

A Modified Partial Product Generator for Redundant Binary Multipliers

Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5 percent). The power-delay product can be reduced by up to 59 percent using the proposed RB multipliers when compared with existing RB multipliers.

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

Design of modified booth encoder with power suppression technique

Design of modified booth encoder with power suppression technique

A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology

In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Different reforms are performed in multiplier architecture. In the first step of multiplier operator, a novel radix-16 modified Booth encoder is presented which reduces the number of partial products efficiently. In this research, we present a new algorithm for partial product reduction in multiplication operations. The algorithm is based on the implementation of compressor elements by means of carry network. The structure of these compressors into reduction trees takes advantage of the modified Wallace tree for integration of adder cells and provides an alternative to conventional operator methods. We show several reduction techniques that illustrate the proposed method and describe carry-skip examples that combine dynamic CMOS with classic conventional compressors in order to modify each scheme. In network multiplier, a novel low power high-speed adder cell is presented which uses 14 transistors in its structure. Critical path is minimized to reduce latency in whole operator architecture. Final adder of multiplier uses an optimized carry hybrid adder. The presented final adder network uses dynamic CMOS technology. It sums two final operands in a very efficient way, which has significant effect in operator structure. Presented multiplier reduces latency by 12%, decreases transistor count by 8% and modifies noise problem in an efficient way in comparison with other structures.