Modern SoCs Research Articles

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm2. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.

Power and area optimisation in heterogeneous 3D networks-on-chip architectures

Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. However, the vertical interconnections between layers is more power and area hungry compared to 2D interconnections. In this paper we propose area efficient and low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D homogeneous NoC with bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in power and area efficiency of the NoC resources, respectively.

A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time program trace compressor, named trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the trace compressor, named the online mode, or exclusively as the trace compressor, named the bypass mode. The RTL implementation of a 4 KB trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address trace as well.

Power-efficient deterministic and adaptive routing in torus networks-on-chip

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual channels is important since it has a direct effect on the power consumption of NoCs. In this paper, we propose a novel systematic approach for designing deadlock-free routing algorithms for torus NoCs. Using this method a new deterministic routing algorithm (called TRANC) is proposed that uses only one virtual channel per physical channel in torus NoCs. We also propose an algorithmic mapping that enables extracting TRANC-based routing algorithms from existing routing algorithms, which can be both deterministic and adaptive. The simulation results show power consumption and performance improvements when using the proposed algorithms.

Application driven network-on-chip architecture exploration & refinement for a complex SoC

This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris. Section 2 summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Section 3 describes the proposed top-down approach, based on the progressive refinement of the NoC description, from its functional specification (Sect. 4) to its verification (Sect. 8). The approach is illustrated by a typical use-case of a NoC embedded in a hand-held gaming device. The methodology relies on the definition of the performance behavior and expectation (Sect. 5), which can be early and efficiently simulated against various NoC architectures. The system architect is then able to identify bottle-necks and converge towards the NoC implementation fulfilling the requirements of the target application (Sect. 6).

An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (aHb multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13-m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%-96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

Buffer Planning for IP Placement Using Sliced-LFF

IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7% and 37.1% in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.

Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control

Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. In this paper, we propose a new architecture that significantly reduces the array switching power for SRAM. The proposed architecture combines built-in self-test and digitally controlled delay elements to reduce the wordline pulsewidth for memories while ensuring correct read operations, hence reducing the switching power. Monte Carlo simulations using a 1-Mb SRAM macro in an industrial 45-nm technology are used to verify the power saving for the proposed architecture. For a 48-Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it an attractive solution for 45-nm-and-below technologies.

An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model

Embedded memories have been used extensively in modern SoC designs. In order to estimate the power consumption of an entire design correctly, an accurate memory power models are needed. However, the memory power model that is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The proposed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

The exploration of the design space for heterogeneous reconfigurable systems on chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks, ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy, first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept.

High-resolution flash time-to-digital conversion and calibration for system-on-chip testing

Verification of timing performance in systems-on-chip (SoCs) is becoming more difficult as clock frequencies and levels of integration increase. As a result, on-chip timing measurement has become a very attractive alternative for validation of these systems because it helps to overcome the bandwidth and test access limitations inherent in SoC environments. Flash time-to-digital converters (TDCs) are well suited for use in on-chip timing measurement systems because they can be operated at high speeds, offer low test time and are relatively easy to integrate. However, clock jitter in modern SoCs is often of the same order of magnitude as the temporal resolution of the TDC itself. Therefore, techniques are required to increase TDC resolution while ensuring timing accuracy. A high-resolution flash TDC is presented that exploits the random offsets on flip-flops or arbiters to perform time quantisation. Also described is a novel technique based on additive temporal noise to accurately calibrate this measurement device. Simulation and experimental results reveal that the latter method can calibrate the high-resolution flash TDC down to 5 ps within reasonable error limits. In addition, accurate timing measurement of jitter below 10 ps has been experimentally validated using a high-resolution flash TDC fabricated in a 0.18-µm CMOS process.

An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

Modern SoC architectures manufactured at ever-decreasing geometries use multiple embedded memories. Error detection and correction codes are becoming increasingly important to improve the fault tolerance of embedded memories. This article focuses on automatically optimizing classical Reed-Solomon codes by selecting the appropriate code polynomial and set of used symbols.

ChronoSym: a new approach for fast and accurate SoC cosimulation

The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications.

STRATEGIES FOR RECHRISTIANIZATION. POLITICAL RHETORIC OF THE NORWEGIAN HOME MISSION IN THE 1920’s

The paper discusses the strategies and the rhetorical elements of the Norwegian Inner Mission during a period of political and cultural conflict the 1920’s and 1930’s.Special attentions paid to understanding the ambivalence between premodern values and modern strategies as they were expressed by one of the leaders of one of the inner mission organisations, professor of theology Ole Hallesby (1879 –1961).In his th nking, the explicit aim of the nner mission activities was the rechristianization of Norway, the means were actions organised according to the modern soc ety, but the cultural and soc al ideal was the non-secularzed, premodern Norway – as opposed to urban pluralism. Probably, this ambivalence made the inner mission strategy a political failure.