Modern Processor Architectures Research Articles

Using hardware-transactional-memory support to implement speculative task execution

Loops take up most of the time of computer programs, so optimizing them so that they run in the shortest time possible is a continuous task. However, this task is not negligible; on the contrary, it is an open area of research since many irregular loops are hard to parallelize. Generally, these loops have loop-carried (DOACROSS) dependencies and the appearance of dependencies could depend on the context. Many techniques have been studied to be able to parallelize these loops efficiently; however, for example in the OpenMP standard there is no efficient way to parallelize them. This article presents Speculative Task Execution (STE), a technique that enables the execution of OpenMP tasks in a speculative way to accelerate certain hot-code regions (such as loops) marked by OpenMP directives. It also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for executing tasks speculatively and describes a careful evaluation of the implementation of STE using HTM on modern machines. In particular, we consider the scenario in which speculative tasks are generated by the OpenMP taskloop construct (Speculative Taskloop (STL)). As a result, it provides evidence to support several important claims about the performance of STE over HTM in modern processor architectures. Experimental results reveal that: (a) by implementing STL on top of HTM for hot-code regions, speed-ups of up to 5.39× can be obtained in IBM POWER8 and of up to 2.41× in Intel processors using 4 cores; and (b) STL-ROT, a variant of STL using rollback-only transactions (ROTs), achieves speed-ups of up to 17.70× in IBM POWER9 processor using 20 cores.

A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

SummaryThis article presents a new Domain Specific Embedded Language (DSEL) dedicated to Software‐Defined Radio (SDR). From a set of carefully designed components, it enables to build efficient software digital communication systems, able to take advantage of the parallelism of modern processor architectures, in a straightforward and safe manner for the programmer. In particular, proposed DSEL enables the combination of pipelining and sequence duplication techniques to extract both temporal and spatial parallelism from digital communication systems. We leverage the DSEL capabilities on a real use case: a fully digital transceiver for the widely used DVB‐S2 standard designed entirely in software. Through evaluation, we show how proposed software DVB‐S2 transceiver is able to get the most from modern, high‐end multicore CPU targets.

Distributed primal outer approximation algorithm for sparse convex programming with separable structures

This paper presents the distributed primal outer approximation (DiPOA) algorithm for solving sparse convex programming (SCP) problems with separable structures, efficiently, and in a decentralized manner. The DiPOA algorithm development consists of embedding the recently proposed relaxed hybrid alternating direction method of multipliers (RH-ADMM) algorithm into the outer approximation (OA) algorithm. We also propose two main improvements to control the quality and the number of cutting planes that approximate nonlinear functions. In particular, the RH-ADMM algorithm acts as a distributed numerical engine inside the DiPOA algorithm. DiPOA takes advantage of the multi-core architecture of modern processors to speed up optimization algorithms. The proposed distributed algorithm makes practical the solution of SCP in learning and control problems from the application side. This paper concludes with a performance analysis of DiPOA for the distributed sparse logistic regression and quadratically constrained optimization problems. Finally, the paper concludes with a numerical comparison with state-of-the-art optimization solvers.

Fast and Portable Concurrent FIFO Queues With Deterministic Memory Reclamation

In this article we present an algorithm for a high performance, unbounded, portable, multi-producer/multi-consumer, lock-free FIFO (first-in first-out) queue. Aside from its competitive performance on current hardware, it is further characterized by its integrated memory reclamation mechanism, which is able to reliably and deterministically de-allocate nodes as soon as the final operation with a reference has concluded, similar to reference counting. This differentiates our approach from most other lock-free data structures, which usually require external (generic) memory reclamation or garbage collection mechanisms such as hazard pointers. Our deterministic memory reclamation mechanism completely prevents the build up of memory awaiting reclamation and is hence very memory efficient, yet it does not introduce any substantial performance overhead. By utilizing concrete knowledge about the internal structure and access patterns of our queue, we are able to construct and constrain the reclamation mechanism in such a way that keeps the overhead for memory management almost entirely out of the common fast path. The presented algorithm is portable to all modern 64-bit processor architectures, as it only relies on the commonly available and lock-free atomic synchronization primitives compare-and-swap and fetch-and-add.

A theory of transaction parallelism in blockchains

Decentralized blockchain platforms have enabled the secure exchange of crypto-assets without the intermediation of trusted authorities. To this purpose, these platforms rely on a peer-to-peer network of byzantine nodes, which collaboratively maintain an append-only ledger of transactions, called blockchain. Transactions represent the actions required by users, e.g. the transfer of some units of crypto-currency to another user, or the execution of a smart contract which distributes crypto-assets according to its internal logic. Part of the nodes of the peer-to-peer network compete to append transactions to the blockchain. To do so, they group the transactions sent by users into blocks, and update their view of the blockchain state by executing these transactions in the chosen order. Once a block of transactions is appended to the blockchain, the other nodes validate it, re-executing the transactions in the same order. The serial execution of transactions does not take advantage of the multi-core architecture of modern processors, so contributing to limit the throughput. In this paper we develop a theory of transaction parallelism for blockchains, which is based on static analysis of transactions and smart contracts. We illustrate how blockchain nodes can use our theory to parallelize the execution of transactions. Initial experiments on Ethereum show that our technique can improve the performance of nodes.

Linear and nonlinear solvers for simulating multiphase flow within large-scale engineered subsurface systems

Multiphase flow simulation is well-known to be computationally demanding, and modeling large-scale engineered subsurface systems entails significant additional numerical challenges. These challenges arise from: (a) the presence of small-scale discrete features like shafts, tunnels, waste packages, and barriers; (b) the need to accurately represent both the waste form processes at the small spatial scale of the repository and the large-scale transport processes throughout heterogeneous geological formations; (c) the strong contrast in material properties such as porosity and permeability, as well as the nonlinear constitutive relations for multiphase flow. Numerical solution entails discretization of the coupled system of nonlinear governing equations and solving a linear system of equations at each Newton–Raphson iteration. Practical problems require a very large number of unknowns that must be solved efficiently using iterative methods in parallel on high-performance computers. The unique challenges noted above can lead to an ill-conditioned Jacobian matrix and non-convergence with Newton’s method due to discontinuous nonlinearity in constitutive models. Moreover, practical applications can require numerous Monte-Carlo simulations to explore uncertainly in material properties, geological heterogeneity, failure scenarios, or other factors; governmental regulatory agencies can mandate these as part of Performance Assessments. Hence there is a need for flexible, robust, and computationally efficient methods for multiphase flow in large-scale engineered subsurface systems.We apply the open-source simulator PFLOTRAN to the practical problem of performance assessment of the US DOE Waste Isolation Pilot Plant (WIPP) site. The simulator employs a finite volume discretization and uses the PETSc parallel framework. We evaluate the performance of several preconditioners for the iterative solution of the linearized Jacobian system; these range from stabilized-biconjugate-gradient with block-Jacobi preconditioning (BCGS) to methods adopted from reservoir modeling, such as the constrained pressure residual (CPR) two-stage preconditioner and flexible generalized residual solver (FGMRES). We also implement within PETSc the general-purpose nonlinear solver, Newton trust-region dogleg Cauchy (NTRDC), which truncates the Newton update or modifies the update with a Cauchy solution that is within the quadratic model trust-region of the objective function. We demonstrate the effectiveness of each method for a series of test problems with increasing difficulty. We find that the NTRDC and FGMRES-CPR-ABF (FCA) preconditioners generally perform best for the test problem having the extreme nonlinear processes, achieving a 50x speed-up compared with BCGS. The most ill-conditioned and extreme nonlinear simulations do not converge with BCGS (as one may expect), but they do complete the simulation with NTRDC and FCA. We also investigate the strong scalability of each method and demonstrate the impact of node-packing upon parallel performance on modern processor architectures.

РЕАЛІЗАЦІЯ ФІЛЬТРА З ПОСТФІЛЬТРАЦІЙНИМ ПРИЙНЯТТЯМ РІШЕННЯ НА МІКРОПРОЦЕСОРНИХ АРХІТЕКТУРАХ З ВЕКТОРНИМ РОЗШИРЕННЯМ ДЛЯ ЗАБЕЗПЕЧЕННЯ ПОКАЗНИКІВ ЕФЕКТИВНОСТІ СУДОВОЇ ЕКСПЕРТИЗИ

Наводяться результати досліджень засобів забезпечення показників ефективності судової експертизи зображень, у тому числі й цифрових. Проводиться аналіз основних завдань, що стоять при експертизі зображень, і методи їх розв’язання. Основною проблемою таких досліджень є недостатня автоматизація процесу обробки зображень при експертизі. Об’єктом дослідження є процес фільтрації зображень, предметом досліджень – фільтри, які використовуються при обробці зображень. В результаті аналізу реалізацій детекторів шуму встановлено, що вони є обчислювально складними. А апаратні витрати на реалізацію алгоритму на сучасних мікропроцесорах і програмованих інтегральних схемах можуть істотно обмежувати застосування таких алгоритмів у додатках, що вимагають обробки в реальному часі. Метою статті є побудова швидкодіючої реалізації фільтра з постфільтраційним прийняттям рішення на сучасних процесорних архітектурах. Наведено результати аналізу можливості використання векторних інструкцій сучасних процесорних архітектур, розглянуто алгоритми векторизації сортування для ефективної реалізації підпрограми пошуку медіанного значення всередині поточного і проведено моделювання фільтра з постфільтраційним прийняттям рішення з метою з’ясування придатності для використання в задачах реального часу. В результаті проведених досліджень вперше запропоновано метод векторизованої реалізації фільтра з постфільтраційним прийняттям рішення, придатний для процесорів з набором команд SIMD ARM NEON, Intel SSE або AVX; розглянуто використання сортувальних мереж як алгоритму пошуку медіани для процесорів з векторним розширенням; вперше побудовано реалізацію фільтра описаним методом для процесора ARM Cortex-A9 в складі SOC Intel Cyclone® V SE 5CSEBA6U23I7NDK; проведено моделювання роботи фільтра на ARM Cortex-A9. Швидкість обробки зображення 512x512 пікселів становила понад 500 кадрів на секунду. Швидкість обробки напівтонових зображень FullHD – понад 60 кадрів на секунду.

Mathematics and Speed for Interval Arithmetic

After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set ¯IR of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of ¯IF, which are executable on the computer. Arithmetic for intervals of ¯IF forms an exception free calculus, i.e., arithmetic operations for intervals of ¯IF always lead to intervals of ¯IF again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

Кэширование данных в мультиконтейнерных системах

Today, virtualization is a key technology for cloud computing and modern data centers, providing scalability and security, managing the global IT infrastructure and reducing costs. Among the methods of virtualization, the most popular was containerization, that is the isolation of related groups of linux processes that share a common Linux kernel. Containerization is more profitable that classical hardware virtualization because of compactness of containers and lower overhead costs of memory, disk, CPU. However, in comparison with classical architectures without process isolation containers can cost more, and in any case, the industry is waiting for additional optimization – the speed of launch, saving memory and disk space and other resources. Different caching techniques can help in this, because Caching is the oldest mechanism of increasing software productivity without radical modification of algorithms and hardware. However, there are a lot of architectural and engineering tradeoffs. Here we will consider modern scientific and technical approaches to their solution in different aspects – acceleration of launch, optimization of shared usage, acceleration of building container images, as well as some security problems caused by aggressive caching in modern processor architectures. And in some use cases for multi-container systems performance and latency are not important, but we have to ensure the maximum load of physical servers. In these cases, the algorithms of planning and placement of containers are relevant, and we give an overview of theoretical work on this topic.

Two-dimensional line segment–triangle intersection test: revision and enhancement

Two-dimensional line segment–triangle intersection test is a part of some 3D triangle–triangle intersection test algorithms. It is the kind of algorithms dealing with intersection of one triangle and line segment obtained as the intersection of the other triangle with the plane which the first triangle lies on. There appeared a number of algorithms each proclaiming its efficiency against to its predecessors with respect to the number of operations. In the paper, we seek out the minimal set of operations. Applying divide and conquer paradigm, we split the operations needed into (a) fixed part consisting of core arithmetic operations and (b) variable part dealing with logical reasoning. As we come to the set of core arithmetic operations that cannot be further minified we realize previous algorithms come to the same set in spite of their different strategies. Further improvement we sought in the area of modern processor architectures. We exploit modern CPU’s parallel processing capabilities like Single instruction, multiple data vectorization, parallel—out-of-order execution and branch prediction and enlighten their strengths and weaknesses for usage in this type of algorithms.

An efficient SIMD compression format for sparse matrix‐vector multiplication

SummarySparse matrix‐vector multiplication (SpMV) is an essential kernel in sparse linear algebra and has been studied extensively on all modern processor and accelerator architectures. Compressed Sparse Row (CSR) is a frequently used format for sparse matrices storage. However, CSR‐based SpMV has poor performance on processors with vector units. In order to take full advantage of SIMD acceleration technology in SpMV, we proposed a new matrix storage format called CSR‐SIMD. The new storage format compresses the non‐zero elements into many variable‐length data fragments with consecutive memory access addresses. Thus, the data locality of sparse matrix A and dense vector x expands and the floating‐point operations for each fragment can be completely calculated by vectorized implementation on wide SIMD units. Our experimental results indicate that CSR‐SIMD has better storage efficiency and low‐overhead for format conversion. Besides, the new format achieves high scalability on wide SIMD units. In comparison with the CSR‐based and BCSR‐based SpMV, CSR‐SIMD obtains better performance on FT1500A, Intel Xeon, and Intel Xeon Phi.

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.

Global Data Access Optimization Via Load/Store Instruction Extension

The widening gap between processor speed and memory latency makes memory accesses become a major performance bottleneck for modern processor architectures. Eliminating the memory access and improving the program locality may help to improve the performance. This paper proposes the extension design of load and store instructions, describes the hardware/software cooperative optimization idea for global data access. The research work is based on the synthetic analysis of program data access behavior and compiler optimization ability observation, which has a great influence on the design decision. Compared with the popular GP-addressing technique, our method may not only save the dedicated registers, but also eliminate the overhead of calling functions in dynamic shared objects. Experiment results show an average reduction of 5.92% in dynamic memory access instructions and an average improvement by 2.16% in code size for SPEC programs.

On the injection of hardware faults in virtualized multicore systems

Virtualized multicore systems represent an emerging computing paradigm in the critical systems industry. Virtualization-based solutions leverage the different cores of the processor to run operating systems and applications within separate partitions, to support the development of parallel mixed-criticality systems, and to improve fault-tolerance by protecting and isolating the operating environments. The critical systems industry is subjected to international standards, which recommend fault injection as a mean to contribute with evidence to safety cases. This paper proposes a framework to inject hardware faults in virtualized multicore systems. Our proposal capitalizes on the error reporting architecture of modern processors and allows injecting faults both at hypervisor- and guest-OS-level. We implement the framework in the context of the widely used Intel Core i7 processor and Xen hypervisor. We demonstrate the use of the framework by means of about 60,000 injection experiments in a Linux-based virtualized multicore system installation.

The role of index compression in score-at-a-time query evaluation

This paper explores the performance of top k document retrieval with score-at-a-time query evaluation on impact-ordered indexes in main memory. To better understand execution efficiency in the context of modern processor architectures, we examine the role of index compression on query evaluation latency. Experiments include compressing postings with variable byte encoding, Simple-8b, variants of the QMX compression scheme, as well as a condition that is less often considered--no compression. Across four web test collections, we find that the highest query evaluation speed is achieved by simply leaving the postings lists uncompressed, although the performance advantage over a state-of-the-art compression scheme is relatively small and the index is considerably larger. We explain this finding in terms of the design of modern processor architectures: Index segments with high impact scores are usually short and inherently benefit from cache locality. Index segments with lower impact scores may be quite long, but modern architectures have sufficient memory bandwidth (coupled with prefetching) to "keep up" with the processor. Our results highlight the importance of "architecture affinity" when designing high-performance search engines.

Reducing Competitive Cache Misses in Modern Processor Architectures

The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This technique enables competitive access to the entire cache memory when there is a hit - but, if there are cache misses, memory data (by using replacement techniques) is put in a virtual part given to threads, so that competitive cache misses are avoided. By using a simulator tool, the results show a decrease in the number of cache misses and performance increase for up to 15%. The conclusion that comes out of this research is that cache misses are a real challenge for future processor designers, in order to hide memory latency.

Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems

A detailed analysis of power consumption at low system levels becomes important as a means for reducing the overall power consumption of a system and its thermal hot spots. This work presents a new power estimation method that allows understanding the power breakdown of an application when running on modern processor architecture such as the newly released Intel Skylake processor. This work also provides a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power and performance breakdowns, as well as few interesting case studies.

Application of binary descriptors to multiple face tracking in video surveillance systems

Subject of Research. The paper deals with the problem of multiple face tracking in a video stream. The primary application of the implemented tracking system is the automatic video surveillance. The particular operating conditions of surveillance cameras are taken into account in order to increase the efficiency of the system in comparison to existing general-purpose analogs. Method. The developed system is comprised of two subsystems: detector and tracker. The tracking subsystem does not depend on the detector, and thus various face detection methods can be used. Furthermore, only a small portion of frames is processed by the detector in this structure, substantially improving the operation rate. The tracking algorithm is based on BRIEF binary descriptors that are computed very efficiently on modern processor architectures. Main Results. The system is implemented in C++ and the experiments on the processing rate and quality evaluation are carried out. MOTA and MOTP metrics are used for tracking quality measurement. The experiments demonstrated the four-fold processing rate gain in comparison to the baseline implementation that processes every video frame with the detector. The tracking quality is on the adequate level when compared to the baseline. Practical Relevance. The developed system can be used with various face detectors (including slow ones) to create a fully functional high-speed multiple face tracking solution. The algorithm is easy to implement and optimize, so it may be applied not only in full-scale video surveillance systems, but also in embedded solutions integrated directly into cameras.

Centralized MAC protocol for hierarchical caching processors

The subject of research is the architecture of modern processors with hierarchical organization of cache subsystem. Analysis of implementation possibility of wireless connectivity between cores and Level 3 cache has been carried out. In order tospecify the requirements to wireless communication channel, communication in modern general-purpose processors has been explored by an example of Intel Core i7 (Haswell). Interaction model of cache subsystem components has been developed, and on its basis interaction characteristics between them are being evaluated. Analysis of the model shows that the latency of cache line transmission via the proposed channel is about 0.26 nanoseconds, which correlates well with the latency of L1 cache (about 2 nanoseconds). Also, wireless channel satisfies the distance requirements, giving the possibility for data transmission upto 3 centimeters, as well as power requirements with consumption of 1 uW. The result of research is the developed medium access protocol for wireless connectivity between computational cores and Level 3 cache. To account for required simplicity of implementation and efficiency of operation, it is proposed to use the single frequency range for all radio interfaces and time division multiple access scheme with prescribed fields for addressing and data. The paper deals with protocol data unit structure, which is used for communication between units. Possibility of shared time counter creationis used for synchronization between units. Time division duplex with possibly dynamic non-equal time shares is used to organize uplink and downlink communications. Time division mechanism gives the possibility for the system to adapt to load irregularities between the cores through allocation of various amounts of time slots for each core.

Fast bitwise pattern-matching algorithm for DNA sequences on modern hardware

We introduce a fast bitwise exact pattern-matching algorithm, which speeds up short-length pattern searches on large-sized DNA databases. Our contributions are two-fold. First, we introduce a novel exact matching algorithm designed specifically for modern processor architectures. Second, we conduct a detailed comparative performance analysis of bitwise exact matching algorithms by utilizing hardware counters. Our algorithmic technique is based on condensed bitwise operators and multifunction variables, which minimize register spills and instruction counts during searches. In addition, the technique aims to efficiently utilize CPU branch predictors and to ensure smooth instruction flow through the processor pipeline. Analyzing letter occurrence probability estimations for DNA databases, we develop a skip mechanism to reduce memory accesses. For comparison, we exploit the complete \textit{Mus musculus} sequence, a commonly used DNA sequence that is larger than 2 GB. Compared to five state-of-the-art pattern-matching algorithms, experimental results show that our technique outperforms the best algorithm even for the worst-case DNA pattern for our technique.