Modern Metal Oxide Semiconductor Research Articles

Spatial Revelations of Chemical and Electrochemical Kinetics into Defect Generations during Semiconductor Processing

Semiconductor processing is an extreme challenge due to the defect generations at a microscopic scale down to nanometers in size. Over the past several decades, the industry has been constantly experiencing dramatically increased complexities in manufacturing. A production flow is often made up of hundreds of steps and involves a variety of complicated equipment and chemicals. In addition to the common three states (i.e., solid, liquid, gas), plasma has also been extensively used in many steps involved in clean, deposition, and etch. Meanwhile, a lot of incidental events and sources, such as contaminations and problem tools, can readily occur from time to time. The list goes on and on. Consequently, some of these detrimental factors and variances can generate various defects in degrading or even crashing production lines.When a defectivity issue occurs, a failure analysis (FA) is typically initiated for identifying the nature of defects and where and how they are embedded into the device stack. To start with, a voltage or current has to be applied to excite the defective spot for detecting a localized thermal or photonic signal. However, a small voltage application or current injection, even in nano-ampere, can easily destroy a microscopic defect. A subsequent cross-sectioning or delayering, even with great care, may miss the defect. Therefore, to nondestructively visualize defects has been a daunting task, and often concludes with a disappointment. Furthermore, the source or origin of an issue may need to be narrowed down by analyzing big data from many production lots and/or further confirmed by executing several designs of experiments (DOEs). All these steps towards root-cause clarification and process improvement can be time-consuming and costly. In addition, the process interactions among different steps can further weaken or cause inconsistencies to the correlations under extensive reviews.Fifteen years ago, the novel concept of “Micro-View (on spots) ≈ Macro-View (on sites)” was first proposed by conceiving the transportation behavior of chemicals during spin cleaning (after L. Sheng et al., IRPS2006). Since that first success in promptly resolving a gate oxide integrity (GOI) crisis, we’ve been frequently searching for more instances of chemical and electrochemical kinetics being intricately tangled with wafer processing. As a result, we’ve gained broader insights by clarifying and resolving a range of intricate cases due to various defect generations.The gate oxide layer, often representing the smallest feature in modern metal-oxide-semiconductor (MOS) technologies, is critically susceptible to a variety of defectivity issues. Many steps in the frontend-of-line (FEOL) processing, especially at cleaning operations with various wet chemicals, deteriorate the conditions on wafer surface, which later incur defects inside the gate oxide layer as well as along its bottom and top interfaces. Furthermore, various corrosions have also been observed in the backend-of-line (BEOL) metallization, such as for the bimetallic AlCu bonding pads. Driven by the built-in potential differences across semiconductor devices, galvanism is also a common mechanism, which, however, has been far less recognized as in typical alloy materials.In this paper, the unique fundamentals of kinetic phenomena during semiconductor processing will be extensively reviewed for the first time. A comprehensive three-dimensional (3D) view provides the insights into chemical transportations along wafer surface and electrical cross-sections in device stack. In order to vividly illustrate the effectiveness of perceivably connecting these unique dynamics with critical defects generated, several case studies will be provided along complex process flows. Overall, these spatial revelations have made significant contributions to the solid technology development as well as the quality manufacturing of our most advanced high-voltage (HV) mixed-signal integrated circuit (IC) processes and products.

On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.

Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

Lateral non-uniformity (LNU) of gate dielectric has been a serious problem in modern metal-oxide-semiconductor (MOS) devices [1], [2]. It was found the LNU became more severe after adopting the post-metalization annealing (PMA) due to possible spiking of metal. The interface of metal and gate dielectric was believed to be uneven after PMA. In this work, a method to ameliorate the lateral uniformity in MOS capacitors was proposed. By utilizing the anodic oxidation compensation technique to form a compensatory aluminum layer embedded in MOS structure, obvious improvement in lateral oxide uniformity was observed. The schematic of anodic oxidation compensation is shown in Fig. 1. Accordingly, two batches of MOS capacitors with ultra-thin anodic oxide with equivalent oxide thickness (EOT) ranging from 2 nm to 3.4 nm was prepared for comparison. One is denoted as MOS (MOS stands for the simple Al/SiO2/Si(p) structure), while the other one is denoted as EAMOS (EAMOS stands for Al/Al2O3/Al/SiO2/Si(p) structure with compensatory embedded aluminum). From our previous work, it is known that the electrical characteristics of MOS capacitors in accumulation regime are area-dependent [3]. Hence, the electrical characteristics in accumulation regime are practical for examining the degree of LNU. Fig. 2 shows the current-voltage (I-V), current density-voltage (J-V) and capacitance per unit area-voltage (C’-V) characteristics of both devices. It is obvious that the area-dependence is applied much better in EAMOS devices, which clearly indicates the reduction of LNU. Furthermore, in order to verify the uniformity improvement in whole samples, the percentage dispersions of different device areas of current density and capacitance per unit area in accumulation regime with varied EOT’s are illustrated in Fig. 3. In Fig. 3, for each EOT, the quantity of dispersion of MOS devices is larger than the value of EAMOS devices. Fig. 3(a) shows that the average percentage dispersion of MOS devices for capacitance per unit area with various EOT’s is 3.95%, which is larger than the value of 2.28% of EAMOS devices. Fig. 3(b) shows that the average percentage dispersion of MOS devices for current density with various EOT’s is 90.33%, whereas the value of EAMOS devices (27.7%) is much smaller. These results further serve as the evidences of lessening of LNU. In addition, the breakdown behaviors also point out the improvement in oxide uniformity. Fig. 4 shows the characteristics of time-zero dielectric breakdown (TZDB) of thirteen identical devices for both MOS and EAMOS samples. The values of breakdown voltage for EAMOS devices are more consistent (-4 V to -5 V), while the values for MOS devices range from -2.5 V to -5 V, which are comparatively divergent. Furthermore, currents at -2 V and -8 V are more congruous for EAMOS devices. Consequently, these results give another support to the improved oxide uniformity. Finally, benefited from the reduction of LNU, the lateral distribution of vertical electric field must be more uniform. So when biasing at inversion regime, we believed that the induced minority carriers would distributed more uniform in lateral direction. Therefore, the lateral electric field induced by the non-uniformity of minority carriers would be attenuated. So relieved from the disturbance of lateral Coulomb force, the response of minority carriers to the small signal of gate voltage is believed to be more significant in the EAMOS devices than the MOS devices. Fig. 5 shows the capacitance-voltage (C-V) characteristic of both MOS and EAMOS devices with EOT of 3.4 nm and various frequencies. It is obvious that the frequency response of inversion capacitance is more significant for the EAMOS device than the MOS device. This outcome is consistent with the explanation given above, and it is of use for the circuit design consideration in MOS-based devices. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.

Status of Low-Dose Implantation for VLSI

This article describes the current status of implantation in silicon for ion doses up to but not including the onset of the amorphous state. Physical phenomena, applications to VLSI, and equipment issues are discussed and linked from the viewpoint of vertically integrated technologies (see Figure 1). In such a view, engineering applications are the customer of research on phenomena, and the equipment industry is the customer of both the research and applications community. The article highlights areas in phenomena, applications, and equipment requiring particular attention.Studies in physical phenomena associated with ion implantation are motivated by the need for very shallow junctions. The shallowness is limited by ion channeling effects in crystalline silicon (which directly affect the as-implanted impurity profile) and by diffusion (which occurs during implant activation and annealing of damage). The inventory of ion-damage induced defects includes point defects, cluster defects, and dislocations arising from the combination of damage and annealing. A recent survey by Schreutelkamp et al. of low-dose implantation describes advances in characterization of channeling effects, and the formation of dislocation damage which, in turn, impacts thermally processed profiles. These effects need to be understood in terms of modern MOS (metal-oxide-semiconductor) processes.

MOS-Transistor Radiation Detectors and X-Ray Dose-Enhancement Effects

Sandia National Laboratory (SNL) CMOS IC dose detectors and 3N161 MOS Transistors were evaluated as pulsed X-radiation dosimeters and used as monitors to measure doseenhancement effects. Measurements were made in the photon environments from the HydraMITE II, SPR III, MBS and PITHON radiation sources. The dosimeter evaluation data suggest that the 3N161 MOS transistors are useful dosimeters for measuring flash X-ray-induced doses in the oxide layers of modern metal-oxide-semiconductor (MOS) integrated circuits. However, doseenhancement calculations indicate that Monte Carlo codes, using 1-D geometries and calculated source spectra, consistently overpredict measured dose-enhancement ratios by factors as large as two.