Modeling And Analysis Of Real-Time And Embedded Systems Research Articles

A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering.

Electronically Tunable Multifunction Current Mode Filter Employing Grounded Capacitors

The recent advances in Unified Modeling Language (UML) give a valuable milestone for its application to modern embedded systems design space exploration. However, it is essential to remember that UML is unable to solve the difficulty associated with embedded systems analysis, but it only provides standard modeling means. A reliable Design Space Exploration (DSE) process which suits the peculiarities of complex embedded systems design is necessary to complement the use of UML for design space exploration. In this article, we propose a Model Driven Engineering-based (MDE) co-design flow that combines high-level data-intensive application analysis with rapid prototyping. In order to specify the embedded system, our methodology relies on the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) UML profile. Moreover, the present contribution uses the Parameterized and Interfaced Synchronous Dataflow (πSDF) Model-of-Computation (MoC) and a model based on the IP-XACT standard as intermediate levels of abstraction to facilitate the analysis step in the co-design flow. The rapid prototyping process relies on the πSDF graph of the application and a system-level description of the architecture. This paper presents our Hw/Sw co-specification methodology, including its support for gradual refinement of the high-level models towards lower levels of abstraction for design space exploration purposes.

StohMCharts: A Modeling Framework for Quantitative Performance Evaluation of Cyber-Physical-Social Systems

Cyber-physical-social systems (CPSS) have recently gained attention from researchers due to their combination of cyber, physical, and social spaces. Modeling and Analysis of Real-Time and Embedded systems (MARTE) is a Unified Modeling Language (UML) extension profile that supports the specification, design, and verification of Real-Time Embedded Systems (RTES). While MARTE Statecharts can assist in describing CPS, it does not model the uncertainty within a CPSS environment. To enhance the accuracy of CPSS analysis, we propose the stohMCharts (stochastic hybrid MARTE statecharts) modelling framework as an extension of MARTE statecharts for modelling and analyzing stochastic hybrid systems. stohMCharts can model CPSS in a unified manner. Additionally, based on the mapping rules and algorithms, we have developed a tool to convert models built in stohMChart language into Networks Stochastic Hybrid Automata (NSHA) which can be verified by statistical model checker UPPAAL-SMC. We demonstrate the efficiency and accuracy of the framework by applying it to one autonomous driving scenarios.

System-Theoretic Process Analysis Based on SysML/MARTE and NuSMV

Systems Theoretical Accident Model and Process (STAMP), which considers system safety as an emergent property of the system, is a more effective accident/loss causality model for modern complex systems. Based on STAMP, System Theoretical Process Analysis (STPA) has attracted increasing attention as a new approach to hazard analysis, and relevant international standards are being developed. However, STPA is mainly performed manually, leading to inefficiencies, and constructs models in non-standard language, hindering the integration with existing systems engineering. STPA-SN (STPA based on SysML/MARTE and NuSMV) is proposed to build model in SysML, describing the timing with MARTE (Modeling and Analysis of Real-Time and Embedded Systems), transform SysML model into NuSMV model and output loss scenarios automatically with model checker. An application example of STPA-SN is provided to demonstrate potentials for higher efficiency of analysis and for collaboration with SysML-based systems engineering.

Transformation of sequence diagram to timed Petri net using Atlas Transformation Language metamodel approach

AbstractReal‐time systems are complex and composed of time‐bounded events that must satisfy the real‐time constraints for their proper functioning. To cope with the complexity of real‐time systems, model‐driven approaches such as model‐driven architecture (MDA) can be followed, which uses the conceptual models for system representation. This paper presents an MDA‐based automated approach for an early stage performance evaluation and verification of a real‐time system using the Unified Modeling Language (UML)/Modeling and Analysis of Real‐Time and Embedded systems (MARTE) sequence diagram. A metamodel‐based model‐to‐model transformation technique is used for mapping the UML/MARTE sequence diagram into the generalized Petri Net Markup Language (PNML) representation of the timed Petri net model using Atlas Transformation Language (ATL). The derived PNML representation has the advantage to support the interoperability between different Petri net tools when compared over the existing methods that produce tool‐specific representation. The proposed approach enables the system designers to create and evaluate alternate system designs and predict their behavior, contributing to improving the system quality. The contribution of the proposed technique for identifying the optimal system design is analyzed using a real‐time embedded sensor application. The proposed transformation approach is also validated using a real‐time system from the manufacturing domain.

Controlling the Complexity of Hierarchical Scheduling Frameworks

Hierarchical scheduling frameworks are a new scheduling paradigm where multiple system schedules are integrated (one-within-another). HSFs presents a multi-layered complexity problem that system engineers are struggling to contain. A promising trend in the aerospace and defense industry is to employ Digital Engineering’s Model-Based Systems Engineering (MBSE) to deal with the complexity of HSFs. MBSE permits the abstraction of application-specific details that can radically speed up system design exploration. Thus, this paper investigates how the output from an HSF algorithm can be converted into an MBSE modeling language that enables architectural exploration for resource allocation. The Unified Modeling Language (UML) Modeling and Analysis of Real-Time and Embedded Systems (MARTE) Profile is the chosen unified modeling language of MBSE. The modeling language is used with an HSF application for demonstration purposes. The approach in this paper seeks to limit tool use by combining an inline verification method (Genetic Algorithm) with a new MBSE workflow.

An UML Based Performance Evaluation of Real-Time Systems Using Timed Petri Net

Performance is a critical non-functional parameter for real-time systems and performance analysis is an important task making it more challenging for complex real-time systems. Mostly performance analysis is performed after the system development but an early stage analysis and validation of performance using system models can improve the system quality. In this paper, we present an early stage automated performance evaluation methodology to analyse system performance using the UML sequence diagram model annotated with modeling and analysis of real-time and embedded systems (MARTE) profile. MARTE offers a performance domain sub-profile that is used for representing real-time system properties essential for performance evaluation. In this paper, a transformation technique and transformation rules are proposed to map the UML sequence diagram model into a Generalized Stochastic Timed Petri net model. All the transformation rules are implemented using a metamodel based approach and Atlas Transformation Language (ATL). A case study from the manufacturing domain a Kanban system is used for validating the proposed technique.

A security modeling and verification method of embedded software based on Z and MARTE

The existing modeling and verification methods for embedded software are insufficient towards the increasingly prominent security requirements. In this paper, aiming at high security requirements of embedded software, a security modeling and verification framework of embedded software based on semi-formal and formal methods is proposed. An extensible security model ZMsec (Z-MARTE security model), which extends Z with elements of MARTE (Modeling and Analysis of Real-Time and Embedded systems) and FSA (Finite State Automata), is presented to describe three dimensions of software: security usecases, static structures and dynamic behaviors. Further on, this paper designs ZMsecTL (ZMsecTemporal Logic) formulas to describe security properties, and proposes ZMCA (ZMsec Model Checking Algorithm), a security model checking algorithm on ZMsec model, to verify security properties in ZMsecTL formulas. In order to provide an intuitive state transition diagram for model checking, a depth-first ZMsecSD (ZMsecState Diagram) generation algorithm is designed. Drawing on the abstract framework, this paper develops a prototype implementation of ZMV (ZMsec Modeling and Verification tool), a tool for ZMsec integrated with modeling and verification phases. We finally discuss an embedded software example with ZMV, which illustrates and validates the security modeling and verification method proposed in this paper.

A Method for Measuring the Constraint Complexity of Components in Automotive Embedded Software Systems

The rapid growth of software-based functionalities has made automotive Electronic Control Units (ECUs) significantly complex. Factors affecting the software complexity of components embedded in an ECU depend not only on their interface and interaction properties, but also on the structural constraints characterized by a component’s functional semantics and timing constraints described by AUTomotive Open System ARchitecture (AUTOSAR) languages. Traditional constraint complexity measures are not adequate for the components in embedded software systems as they do not yet sufficiently provide a measure of the complexity due to timing constraints which are important for quantifying the dynamic behavior of components at run-time. This paper presents a method for measuring the constraint complexity of components in automotive embedded software systems at the specification level. It first enables system designers to define non-deterministic constraints on the event chains associated with components using the AUTOSAR-based Modeling and Analysis of Real-Time and Embedded systems (MARTE)-UML and Timing Augmented Description Language (TADL). Then, system analysts use Unified Modeling Language (UML)-compliant Object Constraint Language (OCL) and its Real-time extension (RT-OCL) to specify the structural and timing constraints on events and event chains and estimate the constraint complexity of components using a measure we have developed. A preliminary version of the method was presented in M. Garg and R. Lai, Measuring the constraint complexity of automotive embedded software systems, in Proc. Int. Conf. Data and Software Engineering, 2014, pp. 1–6. To demonstrate the usefulness of our method, we have applied it to an automotive Anti-lock Brake System (ABS).

Model checking of MARTE/CCSL time behaviors using timed I/O automata

Abstract Modelling and Analysis of Real-time and Embedded systems (MARTE) as a domain-specific language is widely used for designing, analysing, and the building of cyber physical systems (CPS). It also provides CCSL as a purely declarative language for expressing logical and chronometric constraints on clocks. Although MARTE/CCSL is powerful expressively, it lacks formal semantics-based language support for describing and analysing. Semantic support, such as timed Input/Output automata not only provides modelling and analysis of timing behaviors, it also provides modelling of the Input/Output behaviors in a direct sense compared to timed automata. The Input/Output behavior can verify the casual relationship between components, one of the most important behaviors is the fairness between components. Thus, to improve the capacity of modeling and verification of the MARTE/CCSL behavior model, we present a method to use MARTE/CCSL as a high level specification language for modelling, then mapping MARTE/CCSL behavior model to timed Input/Output automata, then using an integrated tool (UPPAAL-TIGA) to verify the safety, liveness, and fairness thereof. Finally, we demonstrate the proposed transformation method using a Telerobot control system of real-time systems.

Periodic scheduling for MARTE/CCSL: Theory and practice

The UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) is used to design and analyze real-time and embedded systems. The Clock Constraint Specification Language ( ccsl ) is a companion language for MARTE. It introduces logical clocks as first class citizens as a way to formally specify the expected behavior of models, thus allowing formal verification. ccsl describes the expected infinite behaviors of reactive embedded systems. In this paper we introduce and focus on the notion of periodic schedule to allow for a nice finite abstraction of these infinite behaviors. After studying the theoretical properties of those schedules we give a practical way to deal with them based on the executable operational semantics of ccsl in rewriting logic with Maude. We also propose an algorithm to find automatically periodic schedulers with the proposed sufficient condition, and to perform formal analysis of ccsl constraints by means of customized simulation and bounded LTL model checking. • Introduce the notion of periodic scheduling for MARTE/CCSL specifications. • Prove a sufficient condition for deciding on the existence of a periodic scheduling. • Give an executable formal semantics for MARTE/CCSL in Maude. • Illustrate the formal encoding of customized simulation policies for MARTE/CCSL.

Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs

In recent years, the Electronic Design Automation (EDA) community shifted spotlights from performance to energy efficiency. Consequently, energy consumption becomes a key criterion to take into consideration during Design Space Exploration (DSE). Finding a trade-off between energy consumption and performance early in the design flow in order to satisfy time-to-market is a design challenge of EDA tools. In this paper, we propose the Energy-aWAre Rapid Design of MP2SoC (EWARDS) framework. The EWARDS framework aims at exploring, at design time, the performance and energy capabilities of modern Massively Parallel Multi-Processors System-on-Chip (MP2SoC). The key contribution of the proposed framework is the implementation of an energy-aware scheduling process, named P R E E S M P E , that combines state-of-the-art power management techniques together with Clustering-based Scheduling. The scheduling process is integrated into a Model-Driven Engineering (MDE)-based DSE approach to optimize both performance and energy efficiency in MP2SoC. Moreover, EWARDS extends the Modeling and Analysis of Real-Time and Embedded systems (MARTE) profile with power aspects of MP2SoC systems providing a high-level design entry. To demonstrate the efficiency of the proposed approach, we conducted experiments using the H.263 codec and the FFT algorithm. The obtained results demonstrate that the energy-aware scheduling process can effectively save energy in MP2SoC systems. They also confirmed that our MDE-based approach accelerates the DSE process while generating energy-efficient design decisions.

Uncertainty-Wise Cyber-Physical System test modeling

It is important that a Cyber-Physical System (CPS) with uncertainty in its behavior caused by its unpredictable operating environment, to ensure its reliable operation. One method to ensure that the CPS will handle such uncertainty during its operation is by testing the CPS with model-based testing (MBT) techniques. However, existing MBT techniques do not explicitly capture uncertainty in test ready models, i.e., capturing the uncertain expected behavior of a CPS in the presence of environment uncertainty. To fill this gap, we present an Uncertainty-Wise test-modeling framework, named as UncerTum, to create test ready models to support MBT of CPSs facing uncertainty. UncerTum relies on the definition of a UML profile [the UML Uncertainty Profile (UUP)] and a set of UML Model Libraries extending the UML profile for Modeling and Analysis of Real-Time and Embedded Systems (MARTE). UncerTum also benefits from the UML Testing Profile V.2 to support standard-based MBT. UncerTum was evaluated with two industrial CPS case studies, one real-world case study, and one open-source CPS case study from the following four perspectives: (1) Completeness and Coverage of the profiles and Model Libraries in terms of concepts defined in their underlying uncertainty conceptual model for CPSs, i.e., U-Model and MARTE, (2) Effort required to model uncertainty with UncerTum, and (3) Correctness of the developed test ready models, which was assessed via model execution. Based on the evaluation, we can conclude that we were successful in modeling all the uncertainties identified in the four case studies, which gives us an indication that UncerTum is sufficiently complete. In terms of modeling effort, we concluded that on average UncerTum requires 18.5% more time to apply stereotypes from UUP on test ready models.

Towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems

The Clock Constraint Specification Language (CCSL) is a formal language companion to MARTE (shorthand for Modeling and Analysis of Real-Time and Embedded systems), a UML profile used to facilitate the design and analysis of real-time and embedded systems. CCSL is proposed to specify constraints on the occurrences of events in systems. However, the language lacks efficient verification support to formally analyze temporal properties, which are important properties to real-time and embedded systems. In this paper, we propose an SMT-based approach to model checking of the temporal properties specified in Linear Temporal Logic (LTL) for CCSL by transforming CCSL constraints and LTL formulas into SMT formulas. We implement a prototype tool for the proposed approach and use the state-of-the-art tool Z3 as its underlying SMT solver. We model two practical real-time and embedded systems, i.e., a traffic light controller and a power window system in CCSL , and model check LTL properties of them using the proposed approach. Experimental results demonstrate the effectiveness and efficiency of our approach.

Transformation process of RTS scheduling analysis requirements from UML/MARTE to dynamic priority time Petri Nets

The real-time system (RTS) design is a major challenge due to the complexity of the considered application and the appearance of multiprocessor architectures. Most of the research in this area is interested in high abstraction level methods to decrease the design convolution. In particular, the Unified Modeling Language (UML) profiles and the Model Driven Engineering (MDE) aim at being an adequate solution to support the whole life cycle of RTS design with its real-time constraints and performance issues. Based on MDE and the Modeling and Analysis of Real-Time and Embedded systems (MARTE) profile, the present manuscript proposes an interactive partitioning scheduling of RTS running on multiprocessor architecture. A special attention is paid to the scheduling analysis step to accelerate the exploration of HW/SW space solution. Starting from a candidate solution modeled with UML activity and annotated with MARTE stereotypes, a mapping process to dynamic priority time Petri Nets (dPTPN) was defined. The considered dPTPN is able to prove the schedulability or provide a counterexample to determine the partitions causes of temporal fault. This counterexample presents a useful feedback to the HW/SW space solution explorer in the aim to exclude all solution containing the described partitions.

Applying UML/MARTE on industrial projects: challenges, experiences, and guidelines

Modeling and Analysis of Real-Time and Embedded Systems (MARTE) is a Unified Modeling Language (UML) profile, which has been developed to model concepts specific to Real-Time and Embedded Systems (RTES). In the last 5 years, we have applied UML/MARTE to three distinct industrial problems in three industry sectors: architecture modeling and configuration of large-scale and highly configurable integrated control systems, model-based robustness testing of communication-intensive systems, and model-based environment simulator generation of large-scale RTES for testing. In this paper, we report on our experience of solving these problems by applying UML/MARTE on four industrial case studies. We highlight the challenges we faced with respect to the industrial adoption of MARTE. Based on our combined experience, we derive a framework to guide practitioners for future applications of UML/MARTE in an industrial context. The framework provides a set of detailed guidelines that help reduce the gap between the modeling notations and real-world industrial application needs.

A Formal Transformation Approach for Embedded Software Modeling

Formal specification can enhance the reliability of the embedded system and verify the system properties at the design stage. This paper presents a formal transformation approach for MARTE(Modeling and Analysis of Real Time and Embedded systems) model based on MDA(Model Driven Architecture), and defines the transformation rules of static and dynamic semantic between MARTE model and Object-Z model in term of the formal meta-model. The approach can produce a precise specification and verify the correctness of the system properties before implementing. The paper reports a case study to illustrate formal transformation of MARTE model. It demonstrates that the approach improves the accuracy of system model by transforming it into formal specification and enhances the reliability of software system.

Transformation challenges: from software models to performance models

A software model can be analysed for non-functional requirements by extending it with suitable annotations and transforming it into analysis models for the corresponding non-functional properties. For quantitative performance evaluation, suitable annotations are standardized in the UML Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) and its predecessor, the UML Profile for Schedulability, Performance and Time. A range of different performance model types (such as queueing networks, Petri nets, stochastic process algebra) may be used for analysis. In this work, an intermediate Core Scenario Model (CSM) is used in the transformation from the source software model to the target performance model. CSM focuses on how the system behaviour uses the system resources. The semantic gap between the software model and the performance model must be bridged by (1) information supplied in the performance annotations, (2) in interpretation of the global behaviour expressed in the CSM and (3) in the process of constructing the performance model. Flexibility is required for specifying sets of alternative cases, for choosing where this bridging information is supplied, and for overriding values. It is also essential to be able to trace the source of values used in a particular performance estimate. The performance model in turn can be used to verify responsiveness and scalability of a software system, to discover architectural limitations at an early stage of development, and to develop efficient performance tests. This paper describes how the semantic gap between software models in UML+MARTE and performance models (based on queueing or Petri nets) can be bridged using transformations based on CSMs, and how the transformation challenges are addressed.

Decentralized control for dynamically reconfigurable FPGA systems

The progress in FPGA technology has enabled FPGA-based reconfigurable systems to target increasingly sophisticated applications, which has led to a high control design complexity, resulting in longer design cycles. In this paper, we propose a control design approach for FPGA-based reconfigurable systems aiming at increasing design productivity. This approach is based on a semi-distributed control model that splits different control concerns (monitoring, decision-making and reconfiguration) between autonomous modular controllers and makes use of formalism-oriented design, to decrease the control design complexity and facilitate design verification, reuse and scalability. This model is composed of distributed controllers handling the self-adaptivity of the system reconfigurable regions and a coordinator to respect the system global constraints. To enhance design productivity, the proposed control model is generated automatically using a high-level modeling approach. This approach is based on MDE (Model-Driven Engineering) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard, allowing to make low-level technical details transparent to designers and to automate code generation from high-level models. Experiments on the generated control systems showed that the proposed semi-distributed control model is more flexible, reusable and scalable than the centralized one, at the cost of a slight increase in required hardware resources.

An Approach for Transforming LOTOS Specifications into MARTE Models

The transformation approaches and the traceability approaches from requirements specification to software architecture models are the hot topic, UML profile for MARTE (Modeling and Analysis of Real Time and Embedded systems) is proposed to model the software architectures of real-time and embedded systems, but MARTE models are inaccurate or ambiguous, because they are created based on natural language specifications. In order to obtain more accurate MARTE models, MARTE models need to be given formal semantics. In this paper we use LOTOS (Language of Temporal Ordering Specifications) to describe the requirements specification of real-time systems and propose an approach for generating MARTE models from LOTOS specifications by establishing a mechanism for transforming LOTOS specifications into MARTE models, the MARTE models generated by this approach can increase the reliability for designing the software architectures of real-time systems.