MOSFET Model Research Articles

An analytical I-V model of SiC double-gate junctionless MOSFETs

Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.

Power Semiconductor Junction Temperature and Lifetime Estimations: A Review

The lifetime of power electronic systems is the focus of both the academic and industrial worlds. Today, compact systems present high switching frequency and power dissipation density, causing high junction temperatures and strong thermal fluctuations that affect their performance and lifetime. This paper is a review of the existing techniques for the electro-thermal modelling of Mosfet and IGBT devices regarding lifetime estimation. The advantages and disadvantages of the methodologies used to achieve lifetime prediction are discussed, and their benefits are highlighted. All the factors required to predict power electronic device lifetime, including Mosfet and IGBT electrical models, the computation of power losses, thermal models, temperature measurement and management, lifetime models, mission profiles, cycle counting, and damage accumulation, are described and compared.

Surge current management in Dynamic Reverse Bias reliability testing of WBG devices for automotive application

Efficient management of high-magnitude current spikes during Dynamic Reverse Bias (DRB) reliability testing is critical for early detection of potential issues such as gate oxide degradation in wide bandgap (WBG) devices. This paper addresses the challenges of DRB testing, particularly focusing on current surges caused by rapid dv/dt switching events in WBG devices. Compliance with AQG-324 guidelines, which require a dv/dt of >50 kV/µs, often results in significant current surges due to parasitic capacitance. These surges can reach tens of amperes, leading to excessive self-heating and potentially damaging sensitive measurement circuitry. This study introduces an innovative method to filter out capacitive displacement current spikes without affecting leakage current, reducing surge intensity by over 100 times and enabling efficient DRB testing of up to 1.5 kV WBG devices. The validation process includes simulating a Wolfspeed Power Silicon Carbide (SiC) MOSFET model in LT-Spice and conducting hardware tests on three different 1.2 kV SiC devices from Wolfspeed, Infineon, and Rohm. An optimized PCB design was employed to minimize circuit parasitics, showing good alignment between simulation and hardware testing outcomes.

A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling

A Dynamic Current Sharing Model of Multichip Parallel SiC MOSFETs Considering Layout-Dominated Mutual Inductance Coupling

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

Design of a compact MOSFET model suitable for geometric programming

ABSTRACT The design of analog integrated circuits is a demanding task that involves many constraints and objectives. Also, the transistor models employed must consider high-order physics effects to achieve accurate solutions. Geometric Programming (GP) allows finding the global minimum in optimisation problems, but requires design equations to be in monomial or posynomial form. This work proposes a simplified model inspired on the Advanced Compact MOSFET model tailored to be used in GP problems. The proposed model considers short-channel effects and it is valid in the saturation region with all inversion levels. The equations are presented, first showing the transistor current-voltage characteristic and then the associated capacitances. The validity of the equations is proven by their capacity to fit to the simulated data, achieving a mean error of 0.4% for the main NMOS characteristic. After that, the optimal design of two basic amplifier stages is performed to demonstrate the model usability with GP. The predicted voltage gain and bandwidth of the designed amplifiers are compared with simulations, presenting mean errors of 24.7% and 31.7%, respectively. These errors are low when viewed from a logarithmic perspective and considering the wide design space covered. As GP optimisation guarantees the global minimum location and does not require the usage of a circuit simulator in the loop, the proposed GP-friendly compact model can enable fast and accurate optimisation of analog integrated circuits.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm−3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10−16 A/μm and power dissipation of 9.69 × 10−17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

Modeling of Antenna-Coupled Si MOSFETs in the Terahertz Frequency Range

Modeling of Antenna-Coupled Si MOSFETs in the Terahertz Frequency Range

Impact of Chaos on MOSFET Thermal Stress and Lifetime

The reliability of power electronic switching components is of great concern for many researchers. For their usage in many mission profiles, it is crucial for them to perform for the duration of their intended lifetime; however, they can fail because of thermal stress. Thus, it is essential to analyze their thermal performance. Non-linear switching action, bifurcation and chaotic events may occur in DC-DC power converters. Consequently, they show different behaviors when their parameters change. However, this is an opportunity to study these bifurcation phenomena and the existence of chaos, e.g., in boost converters, on their performance as the effects of load variations (mission profiles) on the system’s behavior. These variations generate many non-linear phenomena such as periodic behavior, repeated period-doubling bifurcations and chaos in the MOSFET drain-source current. Thus, we propose, for the first time, an analysis of the influence of chaos on the junction temperature. First of all, this paper provides a step-by-step procedure to establish an electrothermal model of a C2M0080120D MOSFET with integrated power loss. Then, the junction temperature is estimated by computing the power losses and a thermal impedance model of the switch. Additionally, this model is used to investigate the bifurcation and chaotic behavior of the MOSFET junction temperature. The paper contributes by providing a mathematical model to calculate several coefficients based on experimental data and thermal oscillations. Estimation of the number of cycles to failure is given by the Coffin–Manson equation, while temperature cycles are counted using the rainflow counting algorithm. Further, the accumulated damage results are calculated using the Miner’s model. Finally, a comparison is made between the damage accumulated during different mission profiles: significant degradation of the MOSFET’s lifetime is pointed out for chaotic currents compared to periodic ones.

A Behavior Model of SiC DMOSFET Considering Thermal-Runaway Failures in Short-Circuit and Avalanche Breakdown Faults

Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests.

Two-dimensional analytical model for a non-lightly doped drain SOI MOSFET

A two-dimensional (2D) analytical model considering the effects of the gate oxide region, channel region, and buried oxide region for a non-lightly doped drain (LDD) SOI MOSFET is proposed. The top and bottom surface potential distributions have been derived on the basis of solving 2D Poisson’s equation and using an evanescent mode analysis. The potential distribution, threshold voltage, and threshold voltage roll-off have been verified by Silvaco ATLAS simulated results for the proposed device with different device parameters. The model agrees well with the simulation results under the above-mentioned conditions. Therefore, the analytical model provides the basic designing guidance for non-LDD SOI MOSFETs.

An analytical subthreshold I–V model of SiC MOSFETs

In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short-channel effect. Our subthreshold model becomes complementary to existing models which only describe the I–V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

A Compact Model of High-Voltage MOSFET Based on Electric Field Continuity for Accurate Characterization of Capacitance

A Compact Model of High-Voltage MOSFET Based on Electric Field Continuity for Accurate Characterization of Capacitance

Temperature Scaling and C-V Modeling of SiC Low-Voltage MOSFETs for IC Design

Temperature Scaling and C-V Modeling of SiC Low-Voltage MOSFETs for IC Design

Dynamic Analytical Switching Loss Model of SiC MOSFET Considering Threshold Voltage Instability

Dynamic Analytical Switching Loss Model of SiC MOSFET Considering Threshold Voltage Instability

Three-dimensional Fully-coupled Electromagnetic Field Modeling and Characterization of SiC MOSFET Switching Transients

Three-dimensional Fully-coupled Electromagnetic Field Modeling and Characterization of SiC MOSFET Switching Transients

Fast and Accurate Data Sheet based Analytical Switching Loss Model for a SiC MOSFET and Schottky Diode Half-Bridge

Fast and Accurate Data Sheet based Analytical Switching Loss Model for a SiC MOSFET and Schottky Diode Half-Bridge

Sziklai Pair based Small signal Amplifier with bjt-mosfet Hybrid Unit at 180nm Technology

Two circuit models of Small Signal amplifier, constituted with BJT-MOSFET hybrid unit under Sziklai pair topology are designed and analyzed using ‘PSpice’ and ‘Cadence Virtuoso and Spectre simulation tool (at GPDK 180nm technology)’ respectively. First amplifier (Circuit-1) uses PSpice user-defined model of BJT and MOSFET whereas the second amplifier (Circuit-2) consists of transistors available at GPDK 180nm technology. Circuit-1 can amplify the AC signals of 1mV-1nV range with optimum voltage gain 389.532, 137.570 current gain, 14.464MHz bandwidth and 2.43% THD. However, Circuit-2 can amplify AC signals of 0.1mV-10nV range with 164.018 voltage gain, 32.775 current gain, 11.906 MHz bandwidth, and 13.608E-6% THD. Both the proposed amplifier circuits remove narrow band problem and generate better results than earlier announced small signal Sziklai pair amplifier with BJT-MOSFET hybrid unit in respect of voltage and current gains, bandwidth, THD, and power consumption. Proposed amplifiers successfully address the problem of poor frequency response of small signal Darlington pair amplifier in higher frequency range and narrow bandwidth limitations of small-signal PNP Sziklai pair amplifier. Dependency of the proposed amplifiers at various biasing resistances and performance with temperature variation, noise variation, DC supply variation, and phase variation are also discussed herein. Proposed Circuits display strong dependency over ideal maximum forward beta ‘β’ of NPN transistor, Transconductance ‘VTO’ of P-MOS transistor and additional biasing resistances ‘RA’. Layout of Circuit-2 is found to cover 96.3898µm2 area with 11.32µm length and 8.515µm breadth. Minor percentage variation between pre-layout and post-layout simulation results of Circuit-2 validates the proposed design at GPDK 180nm technology. Monte Carlo and Process Corner analysis are also performed to test the robustness and insensitivity of Circuit-2 against mean value of the parameters and process and mismatch respectively. Performance summary of the proposed circuits and comparison with the recently reported designs shows effectiveness of the proposed circuits in terms of power gain, THD, voltage gain, current gain, input referred noise and power gain. Qualitative analysis of the proposed Circuits recommends its usability as Low Noise Amplifier in the portable RF noise measurement system.

A unified core model of double-gate and surrounding-gate MOSFETs for circuit simulation

This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature.

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

SummaryMetal oxide semiconductor field effect transistors (MOSFETs) are widely used in various power electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for MOSFETs is crucial for EMC analysis of these systems, especially high‐frequency switching circuits. In this paper, a MOSFET EMC modeling method is proposed based on electrical characteristic measurement, simplex optimization, and particle swarm optimization (PSO), to make MOSFET models meet both functionality and EMC analysis requirements. First, systematic methods for extracting SPICE parameters based on physical MOSFETs are presented, including a proposed curve‐fitting method based on PSO for extracting the CDS‐VDS and ID‐VGS characteristic parameters. Second, parametric influence analyses are conducted on some important model parameters, and the law that these parameters affect the EMC of MOSFETs is obtained. Finally, the preliminary MOSFET model was optimized comprehensively using the simplex method. The measured and simulated results are in good agreement in both time domain and frequency domain. It proves that the established model meets the requirements for model accuracy in terms of both EMC and functionality. Therefore, the proposed EMC modeling method is feasible.