Modeling Of Self-heating Effects Research Articles

Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.

Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices

This work pursues a multi-scale modeling approach to combine interconnect and device level simulation in order to study the effects of carrier self-heating and thermal transport on device performance. More specifically, this work will focus on power consumption and heat dissipation in silicon CMOS technology. As device dimensions decrease to the nanometer scale, current density in the device active regions and the circuit interconnects increases [4]. This increase in current density leads to substantial increases in operating temperatures in critical regions of nano-scale electronic devices. We have already shown these effects in n-channel MOSFETs [2], and will continue to explore how this phenomenon affects p-channel MOSFETs and CMOS circuits. This paper presents the methodology used for the study, multi-scale results from the n-channel MOSFET simulations, and preliminary results from the device level p-channel MOSFET simulation. The modeling approach combines an electro-thermal device simulation with a thermal transport solver at the circuit level. The electrical simulation solves Poisson's equations self-consistently coupled with an ensemble Monte Carlo to determine internal electric fields and model electron and hole transport in the device [3]. The thermal simulation solves the energy balance equations for acoustic and optical phonons and uses the phonon energy to determine the lattice temperature [5]. The electro-thermal solver couples these two processes by introducing temperature dependent scattering to the carrier transport solver. Thermal transport can be modeled in a variety of ways: phonon Monte Carlo simulations are necessary for modeling extreme nano-scale and hot-carrier devices, energy balance modeling is used in this study to model thermal transport at the device level, and the Joule heating method commonly used in commercial device simulators is used in this study to model thermal transport at the interconnect level. The thermal modeling in the device and the interconnects is coupled using the device structure itself as an interface: the electro-thermal simulator provides Joule heating terms throughout the device to be used in the Joule heating simulator which in turn gives the temperature profile in the interconnects to be used as a boundary condition in the electro-thermal solver. These simulations are repeated in a self-consistent loop until convergence is achieved [2]. This modeling approach has been successfully applied to n-channel MOSFET devices and the results have been confirmed using a novel experimental approach. Two identical MOSEFTs in either common source or common drain configuration can be biased such that one device is in saturation and one device is in cut-off or sub-threshold region. The device in saturation heats up and the device in sub-threshold is used as a sensor; the temperature in the sensor can be determined using the subthreshold slope [2]. Confirming the simulation results with experimental results for the temperature in the subthreshold device substantiates the accuracy of the methodology for determining the temperature throughout the device [2]. This methodology, now verified by comparison with experimental results for n-channel MOSFETS, will be applied to the study of CMOS circuits.

Self-Heat Characterizations and Modeling of Multifinger nMOSFETs for RF-CMOS Applications

The purpose of this paper is to characterize and model the self-heating effect (SHE) of multifinger n-channel MOSFETs (nMOSFETs). The amount of SHE is small enough not to be analyzed for single-finger bulk CMOS devices. However, SHE should be considered for multifinger nMOSFETs that are mainly used for RF-CMOS applications. The SHE mechanism was analyzed based on a 2-D device simulator. SHE model equations are derived and implemented in the BSIM6 model with Verilog-A language used in a SPICE simulator. The model improves speed and accuracy of multifinger nMOSFETs simulations. To extract thermal resistance and capacitance, an advanced ac conductance method using a vector network analyzer is developed to obtain $I_{{\textrm {ds}}}$ – $V_{{\textrm {ds}}}$ measurement without increasing temperatures with the proposed model and extracted parameters, excellent agreement has been obtained between measurements and simulations in dc and S-parameter domain, whereas the original BSIM6 shows inconsistency between the static dc and the small signal ac simulations due to the lack of SHE. Unlike the widely used subcircuits-based SHE models, including Silicon-On-Insulator MOSFET and power MOSFET models, the proposed SHE model can converge in large-scale circuits even for transient simulations.

An Improved Model of Self-Heating Effects for Ultrathin Body SOI nMOSFETs Based on Phonon Scattering Analysis

Self-heating effects of ultrathin body silicon-on-insulator (SOI) structure are studied by introducing the phonon scattering mechanisms. An improved model of self-heating effects is present considering the heat generation and the thermal diffusion mechanisms. The thermal conductivity parameters are extracted using transient plane source method from the experiment data. The temperature distributions caused by self-heating effects in the silicon layer of SOI nMOSFETs are verified by the numerical Sentaurus TCAD simulation data. The results show that with the thickness of the silicon layer between the gate and the buried oxide decreasing down to sub-20 nm, the phonon scattering rate of free and bound electrons, and the boundary reflection should be taken into consideration in the modeling of self-heating effects.

The importance of thermal conductivity modeling for simulations of self-heating effects in FD SOI devices

In this review paper we want to emphasize the importance of having accurate thermal conductivity models for modeling self-heating effects on the device level. For that purpose, we first consider thin silicon films and calculate (using Sondheimer's approach) their thermal conductivity that incorporates boundary scattering. We then compare the obtained thermal conductivity data with experimental measurements to prove the excellent model agreement with the experimental trends. The parameterized thermal conductivity data are then used in the higher level modeling of self-heating effects in fully-depleted (FD) SOI devices from different technology generations. We find that temperature and thickness dependent modeling of the thermal conductivity is essential for the 25 nanometers technology node. We have also taken into account the anisotropy of the thermal conductivity and modeled devices with (100) and (110) crystallographic orientation. We found out that from thermal point of view the (110) device behaves better, but the (100) device has higher on-current.

Modeling of self-heating effects in polycrystalline silicon thin film transistors

An analytical DC model accounting for the self-heating effect of polycrystalline silicon thin-film transistors (poly-Si TFTs) is presented. In deriving the model for the self-heating effect, the temperature dependence of the effective mobility is studied in detail. Based on the mobility model and a first order approximation, a closed-form analytical drain current model considering the self-heating effect is derived. Compared with the available experimental data, the proposed model, which includes the self-heating and kink effects, provides an accurate description of the output characteristics over the linear, the saturation, and the kink regimes.

A new physics-based self-heating effect model for 4H-SiC MESFETs

A new self-heating effect model for 4H-SiC MESFETs is proposed based on a combination of an analytical and a computer aided design (CAD) oriented drain current model. The circuit oriented expressions of 4H-SiC low-field electron mobility and incomplete ionization rate, which are related to temperature, are presented in this model, which are used to estimate the self-heating effect of 4H-SiC MESFETs. The verification of the present model is made, and the good agreement between simulated results and measured data of DC I – V curves with the self-heating effect is obtained.

Characterization and modeling of bias dependent breakdown and self-heating in GaInP/GaAs power HBT to improve high power amplifier design

It is usual to say that power GaInP/GaAs heterojunction bipolar transistors (HBTs) have many advantages for power amplification at microwave frequencies, because of their high gain and high power density. Furthermore, the possibility of controling the base biasing conditions (voltage, current, self-bias control) compared to a field-effect transistor offers additive degrees of freedom to make a tradeoff between linearity and power-added efficiency. Nevertheless existing devices are limited because of the relatively low breakdown voltage whereas high collector voltage swings are required to achieve high power. This drawback makes them not appropriate for use in the next generation of mobile communication base station or radar systems. Silicon technologies such as LDMOS and III-V devices (MESFET and HFET) present competitive performances in term of high power level but for medium power added efficiency. Important improvements have been made in recent years which make possible large breakdown voltages for GaInP/GaAs HBTs. Breakdown value close to 67 V has been achieved. The aim of this work is to significantly improve the modeling of the breakdown voltage on this type of transistor. Furthermore, the in depth characterization and modeling of self-heating effects have been greatly improved in order to improve thermal management solutions which enable us to enhanced design solutions of HBT high power amplifiers.

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100/spl deg/C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 /spl mu/m. Predictions for a-Si:H TFT's scaled down to 1 /spl mu/m are also provided. The model is suitable for use in device and circuit simulators.

Analysis and modeling of self-heating effects in thin-film SOI MOSFETs as a function of temperature

Self-heating effects are investigated from room down to near liquid helium temperatures in fully depleted N channel thin film SIMOX MOS devices. In addition, a simple theoretical analysis of the self-heating effect is conducted. A procedure for the determination of the thermal resistance and the device temperature rise directly from the static output characteristics is derived. In order to validate this approach, direct self-heating transient measurements are also carried out.

A 6-b, 4 GSa/s GaAs HBT ADC

A GaAs-AlGaAs heterojunction bipolar transistor (HBT) process was developed to meet the speed, gain, and yield requirements for analog-to-digital converters (ADC's). The HBT has current gain of over 100 and f/sub T/ and f/sub MAX/ of over 50 GHz. A 6-b, 4 GSa/s (4 giga-samples/s) ADC was designed and fabricated in this process. The ADC uses an analog folding architecture, includes an on-chip master-slave track-and-hold (T/H) circuit, and provides Gray-encoded digital outputs. The ADC achieves 5.6 effective bits at 4 GSa/s, a faster clock rate than any noninterleaved semiconductor ADC reported to date. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 b) of 1.8 GHz at 4 GSa/s, higher than any published ADC. The chip operates at up to 6.5 GSa/s. GaAs HBT IC's are especially prone to high operating temperatures. This led to reliability problems that were overcome by the use of a fast DC thermal simulator written for this project. A SPICE model for self-heating effects is also described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Two-dimensional simulation of thermal runaway in a nonplanar GTO-thyristor

The problem of electrothermal stability due to different cooling conditions has been investigated by computing the thermal transients in a nonplanar GTO-thyristor. In the first simulation, a steady state occurs with a heat sink removing all the dissipated power. In the second simulation severe thermal runaway is induced due to bad cooling conditions, allowing the analysis of destructive electrothermal interaction. The simulations are based on an advanced model for self-heating effects in silicon devices derived from first principles of irreversible thermodynamics. Self-consistently incorporating a phenomenological model of band gap narrowing in order to take account of heavy doping effects. The system of governing equations is valid in both the steady state and the transient regimes. Four characteristic effects contributing to the heat generation can be identified: Joule heating, recombination heating, Thomson heating, and carrier source heating. Thermal runaway is significantly accelerated in the simulations based on the thermodynamic model of thermoelectric transport compared to a conventional heuristic theory of thermoelectricity. The importance of the entropy balance equation is emphasized in order to derive the mathematical form of the heat flux and the current relations for electrons and holes. Limitations of underlying assumptions are discussed. It is shown that the heat generation implies the Thomson relations.

Modeling of self-heating effects in thin-film soi MOSFET's as a function of temperature

Self-heating phenomena are studied from room down to near liquid helium temperatures in fully depleted N channel thin film SIMOX MOS devices. A simple theoretical analysis of the self-heating effect is worked out. A method for the extraction of the thermal resistance and the device temperature rise directly from the static output characteristics is derived. Also direct self heating transient measurements are conducted in order to confirm our analysis.