Model For Organic Thin-film Transistors Research Articles

Surface-Potential-Based Drain Current Model for Ambipolar Organic TFTs

A surface-potential-based drain current model is presented for ambipolar organic thin-film transistors (OTFTs). First, following the multiple trapping and release (MTR) conduction mechanism, a drain current model is presented for unipolar OTFTs considering exponentially distributed trap state density in the energy gap of an organic semiconductor. Next, from the model for unipolar OTFTs, analyzing electrons or (and) holes in different regimes, the model for ambipolar OTFTs is presented. The presented model can describe the drain current by compact expressions and can estimate the trap states density. The model is verified by available experimental data considering temperature characteristics.

Behavioral modeling for low-voltage pentacene-based OTFTs and their implementations for organic logic circuits

We present a behavioral compact model and its implementation for low-voltage pentacene-based organic thin film transistors (OTFTs) using industry standard BSIM4 (Berkeley Short-channel IGFET Model) in LTspice platform. First, we simplify the number of BSIM4 model parameters according to the device structure. On the other hand, we adapt the BSIM4 mobility equation to OTFT and also involve the off-current using two behavioral current sources. Then, we perform metaheuristics-based optimization to extract the related BSIM4 model parameters together with additional four parameters, introduced in this work, fitting the modified model to the experimental data of an OTFT, using pentacene active layer. Finally, we implement the behavioral compact model in LTspice and validate its usage for low-voltage pentacene-based OTFTs comparing the experimental and modeled current–voltage curves. In this study, we also successfully simulate OTFT implementations of a Pseudo-E inverter, a Pseudo-E NAND gate, and a 1-bit full adder circuit based on NAND gates using our behavioral OTFT model and then investigate the static and dynamic performance parameters of these circuits. The supply voltage is 3 V and maximum frequency of the inputs is 500 Hz in the simulations.

(Invited) Compact Model for Short-Channel Organic Thin-Film Transistors with Extension for Non-Quasistatic Circuit Simulation and Variability Analysis

We present a compact model for organic thin-film transistors (TFTs) that covers both below-threshold and above-threshold operation with a single charge-based current expression [1]. The effect of hopping transport is included by a power-law mobility model. Contact resistances for staggered and coplanar device structures (Fig. 1) are considered, which can be nonlinear in the case of work-function mismatch between contacts and organic semiconductor [2]. Short-channel effects in submicron transistors, such as threshold-voltage roll-off and drain-induced barrier lowering (DIBL), are included [3].From the expression for the accumulated channel charge, a closed-form model for the drain-current variability due to carrier-number and correlated mobility fluctuations has been derived, relating these statistical variations to the trap density in the channel [4].Furthermore, by applying a partitioning scheme, charges are explicitly attributed to the source and drain contacts, allowing the derivation of a charge-based capacitance model valid for quasi-static operation [5]. Charges in the gate-to-contact overlap regions have been included.Utilizing this device model in a transmission-line approach, a circuit simulation including non-quasistatic effects is possible [6]. In the circuit-simulation netlist, the TFT is replaced by a macro model consisting of a finite number of n single transistors, whereby each single transistor represents a section of the intrinsic channel capacitance and a segment of the intrinsic channel resistance. This model is able to capture the charging and discharging of the channel capacitance of each segment through the channel resistance of the adjacent transistors. In this way, the frequency dependence of the node-to-node capacitances of the full device is obtained.The compact model has been implemented in the hardware description language Verilog-A and verified using results of measurements performed on organic p-channel TFTs fabricated on flexible polyethylene naphthalate (PEN) substrates by stencil lithography (Figs. 2, 3). The TFTs consist of 25-nm-thick aluminum gate electrodes, a 5.3-nm-thick hybrid AlOx/SAM gate dielectric, 30-nm-thick gold (Au) source and drain contacts coated with a pentafluorobenzenethiol (PFBT) monolayer, and a 25-nm-thick vacuum-deposited layer of the small-molecule organic semiconductor DPh-DNTT [7,8]. The transmission-line approach has been verified with good accuracy by comparison with frequency-dependent admittance measurements and numerical simulations of the transient switching behavior of organic TFTs. For a transient analysis, the optimum number of segments required to achieve good agreement between the results from the model and those from TCAD simulations is approximately n=6.In conclusion, the model presented here is fully capable of providing accurate results in dc, small-signal ac, and transient circuit simulations, including short-channel effects. Furthermore, the same set of equations allows an estimation of the drain-current variability due to charge trapping. Acknowledgements: This project was funded by the German Federal Ministry of Education and Research ("SOMOFLEX", No. 13FH015IX6), German Research Foundation (DFG) under Grant KL 1042/9-2 (SPP FFlexCom), and EU H2020 RISE ("DOMINO", No. 645760). We acknowledge AdMOS GmbH, Germany for support.

Parameter Extraction and Compact Modeling of OTFTs From 150 K to 350 K

We target the parameter extraction from ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics and modeling of organic thin-film transistors (OTFTs) from 150 K up to 350 K (in two different manufacturing technologies). We also analyze the temperature dependence of the extracted parameters. For that purpose, we used a unified model and parameter extraction method at different temperatures adapted to OTFTs. We validated our model by comparison with experimental ${I}$ – ${V}$ characteristics in both the linear and saturation regimes and ${C}$ – ${V}$ characteristics at different frequencies.

Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Due to the limited lifetime of organic thin-film transistors (OTFTs), it is crucial to predict the degradation of circuit performance at the early stage of design. In this paper, we discuss bias stress voltage degradation of OTFTs. Through the measurements, we show that the gate voltage affects more significantly in the short term device degradation than drain current flow and that the degradation recovers partially when the given bias voltage is removed. We also propose a novel bias stress voltage degradation model that can express the model-parameter degradation and its recovery. The proposed model can fit the temporal shift of the measured model parameters very well.

A Mobility Model Considering Temperature and Contact Resistance in Organic Thin-Film Transistors

Based on the device physics, a mobility model for organic thin-film transistors (OTFTs) is presented considering temperature and contact resistance. As a function of the surface potential, the mobility model including hopping mechanism is able to explain the dependence of temperature and gate bias. The contact resistance is also considered in order to extract the correct mobility. Furthermore, with the assumption that the trapped carrier concentration dominates Poisson’s equation, and combining the mobility model, a DC compact model accounting for contact resistance and temperature is proposed suitable for the temperature scaling from 83 to 295K. Through the extensive comparisons between the model results and the numerical iteration or experimental data, the validity of the mobility and current models is strongly supported.

Compact DC Modeling of Organic Thin-Film Transistors Including Their Parasitic Non-Linear Contact Effects Based on a Novel Extraction Method

This article presents a novel generic method for the extraction of the current–voltage characteristics of organic thin-film transistors (TFTs) that specifically accounts for the individual contributions of the source and drain contacts and their nonlinear behavior. Based on this extraction method, an analytical model has been derived that describes the behavior of the intrinsic TFT and of the source and drain contacts both in the linear and the saturation regimes. The essential feature of the proposed extraction method is that it does not depend on or assume any physical phenomena underlying the electrical characteristics of the contacts. Instead, it extracts the current–voltage characteristics of the contacts which can then be fit to any physics-based TFT model. This is beneficial both for circuit designers and for those developing physics-based TFT models. The proposed extraction method has been applied to organic TFTs fabricated on flexible plastic substrates in the staggered and coplanar device architectures using two different small-molecule organic semiconductors. The compact dc model has been used to simulate organic TFTs with channel lengths ranging from 4 to $100~\mu \text{m}$ and a transimpedance amplifier circuit based on TFTs with different channel lengths, and the results are in good agreement with the measurements.

Evolutionary Computation for Parameter Extraction of Organic Thin-Film Transistors Using Newly Synthesized Liquid Crystalline Nickel Phthalocyanine.

In this work, the topic of the detrimental contact effects in organic thin-film transistors (OTFTs) is revisited. In this case, contact effects are considered as a tool to enhance the characterization procedures of OTFTs, achieving more accurate values for the fundamental parameters of the transistor threshold voltage, carrier mobility and on-off current ratio. The contact region is also seen as a fundamental part of the device which is sensitive to physical, chemical and fabrication variables. A compact model for OTFTs, which includes the effects of the contacts, and a recent proposal of an associated evolutionary parameter extraction procedure are reviewed. Both the model and the procedure are used to assess the effect of the annealing temperature on a nickel-1,4,8,11,15,18,22,25-octakis(hexyl)phthalocyanine (NiPc6)-based OTFT. A review of the importance of phthalocyanines in organic electronics is also provided. The characterization of the contact region in NiPc6 OTFTs complements the results extracted from other physical–chemical techniques such as differential scanning calorimetry or atomic force microscopy, in which the transition from crystal to columnar mesophase imposes a limit for the optimum performance of the annealed OTFTs.

Simulation and Compact Modeling of Organic Thin Film Transistors (OTFTs) for Circuit Simulation

In this paper we present TCAD simulation and compact modeling of OTFTs. Finite element method (FEM) based numerical simulations have been performed using density of state model and field dependent mobility model to simulate the electrical behavior of the OTFT devices. Further Universal Organic Thin Film Transistor (UOTFT) compact model has been applied for simulating the DC I-V characteristics of the device using device modeling software UTMOST-IV. TCAD simulated characteristics and compact model based simulated characteristics were compared and contrasted. Device model parameters were extracted using UOTFT model. Extracted model is applied in designing the OTFT based PMOS-like inverter and hybrid operational amplifier.

(Invited) Compact Modeling of I-V and C-V Characteristics in OTFTs from 125K to 350K

Organic TFTs (OTFs) are very promising devices for flexible, wearable and printed electronics. Nowadays OTFT performances are already comparable to a-Si:H TFTs. In order to design OTFT circuits, physically-based compact models for the OTFT DC, AC and transient characteristics are needed. This requires a correct understanding of the physical effects affecting OTFT behavior. Despite a number of compact I-V models have been presented, only a few C-V models have been published [1-4]. Besides, very few models have considered the temperature dependence, even though temperature analysis is instrumental to identify relevant physical effects. Moreover, most of those temperature studies have been carried out only for I-V characteristics at high temperatures [5] and the very few analysis at low temperatures have not targeted all parameters [6]. In this work, we present a complete study of both current and gate capacitance in OTFTs for temperatures ranging from 150K to 350K. Parameters were extracted using a unified model and extraction method specific to OTFTs, based on assuming an exponential DOS and variable range hopping [7-8]. The dependences of model parameters with the temperature are analyzed. In order to carry out the temperature study of C-V characteristics, we improved an analytical capacitance model [1, 3] for OTFTs in order to be valid from the depletion to the accumulation regime with continuous and smooth regime transitions as well as for the first order gate capacitance derivative. The key parameters used in the capacitance model are the same as those of I-V characteristics and were extracted from them [4, 7]. Furthermore, we show that from the first order gate capacitance model derivative, we can identify the different operating regimes and obtain the threshold voltage () and band-flat voltage ( at different temperatures. We performed measurements on small-molecule OTFTs manufactured in CEA-Liten (Grenoble- France). The OTFTs under study were top gate bottom contact multifingers with and. Our model shows good agreement with the experimental I-V (Fig. 1) and C-V (Fig. 2) characteristics, and the first order capacitance model derivative (Fig. 3) from for temperatures ranging from 120K to 350K, and for frequencies up to 10 kHz. [1] Castro-Carranza, A., et al., (2012). Organic thin-film transistor bias-dependent capacitance compact model in accumulation regime. IET circuits, devices & systems, 6(2), 130-135 [2] Li, L., Marien, et al.,, “Compact Model for Organic Thin-Film Transistors” IEEE Electr Dev Let, vol. 31, no. 3, pp. 210-212, Mar. 2010. [3] Fadlallah, M., et al. “Modeling and characterization of organic thin film transistors for circuit design” J. Appl. Phys, vol. 99, no.104504, May 2006. [4] Estrada, M., et al.,(2013). Frequency and voltage dependence of the capacitance of MIS structures fabricated with polymeric materials. IEEE Transactions on Electron Devices, 60(6), 2057-2063. [5] Estrada, et al., (2010). Modeling the behavior of charge carrier mobility with temperature in thin-film polymeric transistors. Microelectronic Engineering, 87(12), 2565-2570. [6] Haddad, C., et al., Organic Electronics (2018), https://doi.org/10.1016/j.orgel.2018.06.037[7] Estrada, M., at al., (2005). Accurate modeling and parameter extraction method for organic TFTs. Solid-state electronics, 49(6), 1009-1016. [8] Estrada, M.,et al., . (2008). Mobility model for compact device modeling of OTFTs made with different materials. Solid-State Electronics, 52(5), 787-794. Figure 1

(Invited) Physics-Based Compact Model for Organic Thin-Film Transistors with a Universal Charge Expression for Quasi-Static Operation

In this paper, a closed-form model for the drain current and intrinsic capacitances in organic thin-film transistors (TFTs) is presented which is a further improvement and development of the work reported in [1]. The model covers both below-threshold and above-threshold operation with a single charge-based current expression (1) that assumes transport of quasi-free carriers. Parameters Q’ms/d are the densities of the accumulated quasi-free charges at the source and drain end of the channel, respectively. The effect of hopping transport is included in equation (2) by a power-law field-effect mobility model [2]. Rc is the contact resistance, which can be nonlinear in the case of work function mismatch between contacts and organic semiconductor [3]. Drain-current saturation is controlled by parameter λ and expression (3). The current equation provides two views. One view is based on physics and allows for an estimation of the influence of trap densities and interface states on the TFT performance. In this case the accumulated charges are given by equation (4). Here, Nst is the density of traps contributing to the drain current by hopping transport in a channel of thickness dm . N’t,max is the density of filled deep traps and interface states at threshold, having only an influence on the electrostatics. Parameter α is the degradation of the subthreshold slope S given by (5) with respect to an ideal thermal slope of 60 mV/dec at T = 300 K. This expression allows for an extension of the model to include effects such as substrate bending by adapting the trap densities and insulator capacitance according to a geometrical deformation. In this case the mobility model has to take into account a change of the intermolecular spacing. The second view of the model is based on the threshold voltage from a circuit designer’s perspective. Expression (6) for the threshold voltage bridges the two views by allowing for the calculation of the accumulated charges using equation (7). Using the same accumulated charge densities Q’ms/d as employed in the DC current equation, we have derived expressions for the intrinsic capacitances in staggered and coplanar TFTs. Using the Ward-Dutton partitioning scheme [4], the charge density in the channel can be assigned to source, drain and gate. For the integrals in equations (8), (9) and (10), closed-form equations have been derived [5]. Charges in the gate-to-contact overlap regions have been included for both the coplanar and the staggered architecture. This allows the intrinsic capacitances Cij = dQi/dVj in quasi-static operation to be calculated. The model has been implemented in Verilog-A and validated vs. Sentaurus TCAD simulations and TFT measurements (Figs. 1, 2). The results show good agreement. The model uses a unified expression for the accumulated charges in the channel for DC and AC quasi-static operation, which owing to its link to physical parameters such as trap densities can serve as a basis for various extension, e.g., to account for mechanical deformation of flexible organic TFTs. Acknowledgements: This project was funded by the German Federal Ministry of Education and Research ("SOMOFLEX", No. 13FH015IX6) and EU H2020 RISE ("DOMINO", No. 645760). We acknowledge AdMOS GmbH, Germany for support and Keysight Technologies for license donation of IC-CAP.

Compact Modeling of Organic Thin-Film Transistors with Solution Processed Octadecyl Substituted Tetrabenzotriazaporphyrin as an Active Layer

Using 70-nm-thick spin-coated film of newly synthesized octadecyl substituted copper tetrabenzotriazaporphyrin (10CuTBTAP) as an active layer on a highly doped silicon (110) gate electrode substrates, output characteristics and transfer characteristics of bottom-gate bottom-contact organic thin-film transistors have been measured at room temperature. A compact model for thin-film transistors has been employed as a part of circuit design tool to extract device parameters, such as the charge-carrier mobility ${\mu }$ , the threshold voltage $V_{T}$ , and the contact resistances. Parallel measurements and analysis were performed on similarly constructed devices with a copper phthalocyanine(10CuPc) analog. The results reveal that the 10CuPc layer is relatively more susceptible to trapping degradation near the gate region than a 10CuTBTAP layer, which is significant in order to achieve stability in these transistors. The application of the simple square law in the classical MOS model provides a quicker but approximate interpretation of the transistor performance without providing information on the gate-voltage dependence of mobility and the effects of the contact regions. In this paper, the analysis of the contact regions is found to be very important for determining the difference in the performance of two transistors.

A compact model of organic thin-film transistors for display device

Organic transistor has been widely studied for next generation flexible semiconductor process. In this paper, we proposed the organic thin-film transistors (OTFT) model for the display device at the moderately high temperature (above 273K). The model based on hopping theory of Gaussian disordered density-of-states (DOS) considers the dependences relationship of the carrier mobility with temperature and carrier concentrations. Charge transport is controlled by carrier jumps from trap states around the Fermi level to tail trap states at large carrier concentrations. The sub-threshold model is modified using an exponential function to make the model cover all regimes of OTFT operation. A pentacene-based thin film transistor (TFT) model has been designed using Verilog-A language. The model has been verified by device simulations and measurements.

一种精确的有机薄膜晶体管模型参数提取方法研究

一种精确的有机薄膜晶体管模型参数提取方法研究

Analytical Drain Current Model for Organic Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Analytical Drain Current Model for Organic Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Physically Based Compact Mobility Model for Organic Thin-Film Transistor

A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy ( $E_{F}$ ) movement in the bandgap ( $E_{g}$ ) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside $E_{g}$ . The Poole–Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model.

Static and dynamic modeling of organic thin-film transistors for circuit design

A new static and dynamic model for organic thin-film transistors (OTFTs) is proposed. The model incorporates a gate-voltage dependent mobility, drain/source contact series resistance, threshold voltage variation with bias and channel length, and drain induced barrier lowering effect. The model also takes into account all the operating regions and includes static and dynamic characteristics of OTFTs. It is developed using a physical basis where the model's parameters can easily be extracted from the experiment data. The model is suitable for computer aided design applications and has been verified by device simulations and measurements from both p-type and n-type OTFTs.

Characterization and modeling of organic thin-film transistors based π-conjugated small molecule tetraphenyldibenzoperiflanthene: Effects of channel length

P-type organic thin film transistors (OTFTs) with different channel lengths have been fabricated and characterized by thermal evaporation using the small tetraphenyldibenzoperiflanthene (DBP) as an active material on Si/SiO2 substrate. The influence of the channel length on the electrical performance of DBP based organic thin film transistors (DBP-TFTs) prepared with bottom gate-bottom contact in the linear and saturation regimes was systematically examined in this work. All devices showed a significant increase in the output and transfer drain current as the channel lengths were decreased in the linear and saturation regimes. We have reported the variation of the electrical parameters such as transconductance (gm), field effect mobility (μlin and μsat), contacts and total resistances (RC and RT), threshold voltage (Vth), total trap density (Ntrap), subthreshold slope (SS), the interface trap density (Dit), turn-on voltage (Von) and the ratio current (Ion/Ioff) by channel length variation which are extracted from the experimental electrical data current–voltage of DBP-TFTs. We found that the field effect mobility is extremely dependent on the channel length dimensions. We also show that for smaller channel length, it results in a good mobility and a good ratio current of the DBP-TFTs with a short channel length (good saturation mobility and current ratio μsat.max=3×10−2cm2V−1s−1, 1.6×104, respectively, for L=2.5μm). The developed model shows a good agreement with the measured data for all values of channel lengths (L).

SQM-OTFT: A compact model of organic thin-film transistors based on the symmetric quadrature of the accumulation charge considering both deep and tail states

A physically-based compact model of organic thin-film transistors suitable for CAD simulators is proposed. It is worked out by means of a newly developed and particularly simple form of the charge-sheet model: the symmetric quadrature of the accumulation charge. The model is based on the variable-range hopping and accounts for both deep and tail states. It is simple, symmetric, accurately accounts for the below-threshold, linear, and saturation regimes via a unique formulation. The symmetric quadrature is accurate within 5% in all regions of operation and the resulting current model is suitable both for p- and n-type transistors. The model leads to a significant simplification of the drain current and of the quasi-static expressions of the terminal charges based on the Ward–Dutton partition. Finally, the symmetric quadrature leads to an explicit and analytically tractable solution for the surface potential as a function of position in the device channel that can be extremely useful to implement advanced physical effects.

A Surface Potential-Based Gate-Leakage Current Model for Organic Thin-Film Transistors

In this paper, a surface potential-based gate-leakage current (GLC) model for organic thin-film transistors is proposed. It is found that the Poole–Frenkel emission is the main mechanism of GLC, which can be well described by our model for both accumulation and depletion modes. In addition, the source and drain partitions of the channel leakage current can be well explained based on our model. Furthermore, the dependence of GLC on drain voltage, temperature, and material disorder has been discussed in detail, which yields perfect agreement with the experimental data.