Model For Double-Gate Tunnel FETs Research Articles

An analytical charge-based capacitance model for double-gate tunnel FETs

This paper presents an explicit capacitance model with closed-form expressions for double gate tunnel FETs (DG-TFETs). The model is based on a 2-D potential approach, considering the mobile charges in the solution. This model uses a quasi-static approach to obtain terminal capacitances. Charges associated to each electrode are calculated by adopting the Gaussian box, and then the critical terminal capacitances including the input capacitance and the Miller capacitance are analytically expressed. To derive the model, neither fitting parameter nor iterative process is used which means the proposed model can be used for SPICE modeling of TFETs . The presented model provides a physics insight to analyze transient performance in TFET-based circuits. The proposed model is in good agreement with TCAD simulation results. The model is validated for various structural and bias parameters. • Developing a simple and accurate analytical model to capture terminal capacitances of TFETs. • This analytical model can be used as SPICE model to analyze AC performance of TFET-based circuits. • Terminal charges are calculated by developing two-dimensional potential distribution and adopting Gaussian law. • The model results have been compared with simulation results to show accuracy of the model.

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture.

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dg</sub> ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developedwhich enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.

An Analytical Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions and the Channel Mobile Charge Carriers

In this paper, we present an accurate analytical potential model for the double-gate tunnel FETs (DG-TFETs) by solving Poisson’s equation with appropriate boundary conditions. Taking the mobile charge carriers in the channel and the depletion regions inside the source and drain into account, the model predicts the electrostatic potential of the homojunction device in all regions of the device operation more accurately, compared with the predictions of the previously reported models. The potential model is utilized for developing some models for important quantities in TFETs, such as lateral electric field, minimum tunneling length, and drain current. Owing to the physical and analytical nature of the developed models, one can pursue the influence of the transistor parameters on the electrical characteristics of DG-TFETs. To assess the accuracy of the proposed models, the results of the models are compared to those of the numerical simulations and found to be accurately predicting the simulation results for different device parameters.

An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier

This paper presents an analytic model for double-gate tunnel FETs with an exponential barrier. By carrying out the Wentzel-Kramer–Brillouin integral in closed form, an $I$ – $V$ model is formulated in terms of a single integral of a continuous function with respect to energy. The model shows that source degeneracy helps the linear region $I_{\mathbf {ds}}$ – $V_{\mathbf {ds}}$ characteristics, but degrades the saturation current. Also investigated is the role of the effective density of states on the debiasing of $V_{\mathbf {gs}}$ due to channel inversion charge at low $V_{\mathbf {ds}}$ . A high effective density of states is shown to lead to superlinear $I_{\mathbf {ds}}$ – $V_{\mathbf {ds}}$ characteristics.

A 2-D Analytical Model for Double-Gate Tunnel FETs

This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.

Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and high-¿ dielectrics by comparison to 2-D finite-element simulations.