Mobile Processors Research Articles

Parallel Digital Predistortion Design on Mobile GPU and Embedded Multicore CPU for Mobile Transmitters

Digital predistortion (DPD) is a widely adopted baseband processing technique in current radio transmitters. While DPD can effectively suppress unwanted spurious spectrum emissions stemming from imperfections of analog RF and baseband electronics, it also introduces extra processing complexity and poses challenges on efficient and flexible implementations, especially for mobile cellular transmitters, considering their limited computing power compared to basestations. In this paper, we present high data rate implementations of broadband DPD on modern embedded processors, such as mobile GPU and multicore CPU, by taking advantage of emerging parallel computing techniques for exploiting their computing resources. We further verify the suppression effect of DPD experimentally on real radio hardware platforms. Performance evaluation results of our DPD design demonstrate the high efficacy of modern general purpose mobile processors on accelerating DPD processing for a mobile transmitter.

GPGPU Accelerated Deep Object Classification on a Heterogeneous Mobile Platform

Deep convolutional neural networks achieve state-of-the-art performance in image classification. The computational and memory requirements of such networks are however huge, and that is an issue on embedded devices due to their constraints. Most of this complexity derives from the convolutional layers and in particular from the matrix multiplications they entail. This paper proposes a complete approach to image classification providing common layers used in neural networks. Namely, the proposed approach relies on a heterogeneous CPU-GPU scheme for performing convolutions in the transform domain. The Compute Unified Device Architecture(CUDA)-based implementation of the proposed approach is evaluated over three different image classification networks on a Tegra K1 CPU-GPU mobile processor. Experiments show that the presented heterogeneous scheme boasts a 50× speedup over the CPU-only reference and outperforms a GPU-based reference by 2×, while slashing the power consumption by nearly 30%.

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

This paper presents secure data processing with a massive‐parallel single‐instruction multiple‐data (SIMD) matrix for embedded system‐on‐chip (SoC) in digital‐convergence mobile devices. Recent mobile devices are required to use private‐information‐secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end‐user's operation for maintaining the safety condition. To satisfy these security‐related requirements, we propose the interleaved‐bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive‐parallel SIMD matrix processor (MX‐1) for interleaved‐bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization‐approved block ciphers, a data encryption standard (DES), triple‐DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX‐1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX‐1 results are almost constant for all confidentiality modes. The practical‐use energy efficiency of parallel block cipher processing with the evaluation board for MX‐1 was found to be about 4.8 times higher than that of a BeagleBoard‐xM, which is a single‐board computer and uses the ARM Cortex‐A8 mobile processor. Furthermore, to improve the operation of a single‐bit logical function, we propose the development of a multi‐bit logical library for interleaved‐bitslice cipher processing with MX‐1. Thus, the number of clock cycles is the smallest among those reported in other related‐studies. Consequently, interleaved‐bitslice block cipher processing with five confidentiality modes on MX‐1 is effective for the implementation of parallel block cipher processing for several digital‐convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Real-time power-consumption control system for multimedia mobile devices

Energy consumption in battery operated mobile devices is a critical issue. Autonomy periods are increasingly compromised as the complexity of tasks, such as the widespread video decoding ones, is also increased. While new higher-capacity batteries are being developed, techniques to control, i.e. save, the energy consumption can provide a significant benefit. This paper presents the proposal, implementation and test of a real-time closed-loop control system applicable to the power-consumption regulation of multimedia mobile devices. The novel closed loop does not need any specific power sensor but only standard performance monitoring counters (PMCs) available in common mobile processors. From them, the power consumption is estimated with an algorithm to be included into the operating system, along with the control system itself. A theoretical system model has been first developed to (1) enable the design of some controllers and (2) validate the actual results obtained from the control system prototype into a given low-cost development board. These results prove the control-system stability and the comparative suitability of classic controllers to keep the multimedia-system consumption close to the desired value in steady state with settling times as short as a single sample interval.

Offloading to Improve the Battery Life of Mobile Devices

Moving the responsibility for certain computation, communication, and storage operations away from a mobile device's main processor can help save power while simultaneously increasing performance. Here, the authors present an overview of three such offloading techniques. This department is part of a special issue on energy harvesting and power management.

The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

Moore's law, the doubling of transistors per unit area for each CMOS technology generation, is expected to continue throughout the decade, while Dennard voltage scaling resulting in constant power per unit area stopped about a decade ago. The semiconductor industry's response to the loss of Dennard scaling and the consequent challenges in managing power distribution and dissipation has been leveled off clock rates, a die performance gain reduced from about a factor of 2.8 to 1.4 per technology generation, and multi-core processor dies with increased cache sizes. Increased caches sizes offers performance benefits for many applications as well as energy savings. Accessing data in cache is considerably more energy efficient than main memory accesses. Further, caches consume less power than a corresponding amount of functional logic. As feature sizes continue to be scaled down an increasing fraction of the die must be “underutilized” or “dark” due to power constraints. With power being a prime design constraint there is a concerted effort to find significantly more energy efficient chip architectures than dominant in servers today, with chips potentially incorporating several types of cores to cover a range of applications, or different functions in an application, as is already common for the mobile processor market. Digital Signal Processors (DSPs), largely targeting the embedded and mobile processor markets, typically have been designed for a power consumption of 10% or less of a typical x86 CPU, yet with much more than 10% of the floating-point capability of the same technology generation x86 CPUs. Thus, DSPs could potentially offer an energy efficient alternative to x86 CPUs. Here we report an assessment of the Texas Instruments TMS320C6678 DSP in regards to its energy efficiency for two common HPC benchmarks: STREAM (memory system benchmark) and HPL (CPU benchmark)

User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control

Dynamic power management for mobile processors has become very important due to the increased clock speed and number of cores. There have been various power management governors using dynamic voltage and frequency scaling (DVFS). Among them, a user-centric power management has received a lot of attention as a method to save power while maintaining the quality of user experience (UX) referring to the perceived quality of system services to end users. Most user-centric governors have employed DVFS as a method to reduce the power consumption. However, DVFS may not be adequate enough to guarantee UX qualities for all task because the CPU clock speed changed by DVFS can affect all tasks running at the same processor. In order to minimize such inter-task interferences by DVFS, it is necessary to employ task-specific power management methods. This paper shows that CPU bandwidth control developed for CPU resource management within Linux kernel can be employed as a task-specific power management method, and a novel CPU power management scheme employing both DVFS and CPU bandwidth control is proposed. Experimental results show that the proposed governor can reduce the power consumption more than the Ondemand governor can achieve while maintaining the quality of UX.

(Keynote) Development of Magnetic Tunnel Junctions for Stt-Mram Application

A spintronic-based STT-MRAM (Spin-Transfer-Torque Switching type Magnetic Random Access Memory) is one of the promising candidates in the next generation memory thanks to the features such as high density (above giga-bit), non-volatile, low power consumption, high endurance (almost unlimited), high operation speed (~nano sec) and the compatibility with Si technology. Since 2006, we (AIST, Toshiba, Tohoku Univ., Osaka Univ. and Univ.Elec-comm.) have worked on joint projects of STT-MRAM and achieved some key breakthroughs and discoveries that realized high-scalability and the commercialization. This paper presents our R&D activities and prospects for Normally-Off computing [1] using the non-volatility as well as the overall review of STT-MRAM. The first feature of the STT-MRAM is non-volatility which is the most recognized advantage over semiconductor-based DRAMs. It brings low energy operation because the memory cell stores the information without wasting power. Such a feature exhibits in an MTJ (Magnetic Tunnel Junction) which consists of a thin MgO tunnel barrier and a storage and a reference ferromagnetic thin film layers [2]. Then the STT writing technology is also the important phenomenon which was discovered in the last decades. Another breakthrough was the development of the perpendicular-type MTJ (p-MTJ) [3]. Our joint project have firstly realized p-MTJ in 2007, and until now, attained non-volatility, low power STT-switching, high thermal stability and also high magnetoresistance at the same time despite some conflicting conditions. The success of p-MTJ opened up the high scalability above giga-bit. Finally, a recent p-MTJ has met the requirements 30 nm generation or beyond [4]. In the past few years, our challenge for highly scalable STT-MRAM has moved toward further low power and faster p-MTJ, and a new concept of spintronics device. For a cache application, we indeed demonstrated 1/8 power operation of a mobile processor by replacing part of a last level cache by new p-MTJs [5]. For further low power consumption, even if p-MTJ is well optimized, it is difficult to further reduce the switching power in the framework of current-induced driven. To overcome it we have been testing a new concept of the switching, voltage-driven writing technology, in p-MTJs. Although p-MTJ was not fully optimized, we achieved voltage-induced precessional switching with two orders lower power than the current-induced one. So far, STT-MRAM technology has brought some novel functional devices such as a physical random number generator called “Spin-Dice” [7] and a spin-torque oscillator (STO) [8]. Because fabrication process is basically the same as STT-MRAM, on-chip integrated those devices would provide new functions to STT-MRAM: for example, Spin-Dice for the secure data encryption and STO for the inter-chip communication. [1] K. Ando et al., 11th Non-Volatile Memory Symposium (2011) 1. [2] S. Yuasa et al., NMAT 3 (2004) 868. [3] K. Yakushiji et al., APEX 8 (2015) 083003. [4] T. Kishi et al., IEDM (2008) 309.; K. Tsuchida et al., ISSCC (2010) 258.; H. Yoda et al., Curr. Appl. Phys. 10 (2010) E87. [5] K. Ikegami et al., IEDM (2015) 25.1.1. [6] Y. Shiota et al., APEX (2016) 013001.; T. Nozaki et al., APL (2013) 073005. [7] A. Fukushima et al., APEX 7 (2014) 083001. [8] S. Tamaru et al., Sci. Rep. 5 (2015) 18134.; S. Tsunegi et al., APEX 7 (2014) 063009.

Energy efficiency of the simulation of three-dimensional coastal ocean circulation on modern commodity and mobile processors

We analyze energy efficiency of a 3D coastal ocean simulator on Haswell and Cortex-A15 architectures and propose a simple yet effective way to model energy-to-solution on different hardware platforms. The work also demonstrates that using processors from the field of embedded/mobile computing can increase the energy efficiency by 50 %.

PowerChop

On-core microarchitectural structures consume significant portions of a processor's power budget. However, depending on application characteristics, those structures do not always provide (much) performance benefit. While timeout-based power gating techniques have been leveraged for underutilized cores and inactive functional units, these techniques have not directly translated to high-activity units such as vector processing units, complex branch predictors, and caches. The performance benefit provided by these units does not necessarily correspond with unit activity, but instead is a function of application characteristics. This work introduces P ower C hop , a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. P ower C hop adds two small additional hardware units to facilitate phase identification and triggering different power states, enabling the software layer to cheaply track, predict and take advantage of varying unit criticality across application phases by powering gating units that are not needed for performant execution. Through detailed experimentation, we find that P ower C hop significantly decreases power consumption, reducing the leakage power of a hybrid server processor by 9% on average (up to 33%) and a hybrid mobile processor by 19% (up to 40%) while introducing just 2% slowdown.

A Survey of Mobile Device Virtualization

Recent growth in the processing and memory resources of mobile devices has fueled research within the field of mobile virtualization. Mobile virtualization enables multiple persona on a single mobile device by hosting heterogeneous operating systems (OSs) concurrently. However, adding a virtualization layer to resource-constrained mobile devices with real-time requirements can lead to intolerable performance overheads. Hardware virtualization extensions that support efficient virtualization have been incorporated in recent mobile processors. Prior to hardware virtualization extensions, virtualization techniques that are enabled by performance prohibitive and resource consuming software were adopted for mobile devices. Moreover, mobile virtualization solutions lack standard procedures for device component sharing and interfacing between multiple OSSs. The objective of this article is to survey software- and hardware-based mobile virtualization techniques in light of the recent advancements fueled by the hardware support for mobile virtualization. Challenges and issues faced in virtualization of CPU, memory, I/O, interrupt, and network interfaces are highlighted. Moreover, various performance parameters are presented in a detailed comparative analysis to quantify the efficiency of mobile virtualization techniques and solutions.

Compression and Encryption of ECG Signal Using Wavelet and Chaotically Huffman Code in Telemedicine Application.

In mobile health care monitoring, compression is an essential tool for solving storage and transmission problems. The important issue is able to recover the original signal from the compressed signal. The main purpose of this paper is compressing the ECG signal with no loss of essential data and also encrypting the signal to keep it confidential from everyone, except for physicians. In this paper, mobile processors are used and there is no need for any computers to serve this purpose. After initial preprocessing such as removal of the baseline noise, Gaussian noise, peak detection and determination of heart rate, the ECG signal is compressed. In compression stage, after 3 steps of wavelet transform (db04), thresholding techniques are used. Then, Huffman coding with chaos for compression and encryption of the ECG signal are used. The compression rates of proposed algorithm is 97.72 %. Then, the ECG signals are sent to a telemedicine center to acquire specialist diagnosis by TCP/IP protocol.

A neural network accelerator for mobile application processors

Today’s mobile consumer electronics devices, such as smartphones and tablets, are required to execute a wide variety of applications efficiently. To this end modern application processors integrate both general-purpose CPU cores and specialized accelerators. Energy efficiency is the primary design goal for those processors, which has recently rekindled interest in neural network accelerators. Neural network accelerators trade the accuracy of computation for performance and energy efficiency and are suitable for errortolerant media applications such as video and audio processing. However, most existing accelerators only exploit inter-neuron parallelism and leave processing elements underutilized when the number of neurons in a layer is small. Thus, this paper proposes a novel neural network accelerator that can efficiently exploit both inter- and intra-neuron parallelism. For five applications the proposed accelerator achieves average speedups of 126% and 23% over a generalpurpose CPU and a state-of-the-art accelerator exploiting inter-neuron parallelism only, respectively. Besides, the proposed accelerator saves energy consumption by 22% over the state-of-the-art accelerator.

High Speed, High Density Separable Interconnect - 1000 plus I/O ultra-low profile interfaces

HSIO Technologies has developed several interconnect technologies that enable very high speed, fine pitch separable interconnect between a semiconductor package, flex cable or printed circuit assembly and a system level printed circuit board. In basic terms, connector technology has been produced that allows of direct socketing of the SoC, PoP, CPU, RF Module or Memory device directly in a mobile platform in an ultra-low profile interface that also extends to a ganged RF capable interface for flex cable and board to board applications. The technology revolves around matching very small metallic contacts with fusion bonded Liquid Crystal Polymer materials to create a high speed interface on very fine pitch. Applications to be detailed are socketing of mobile processors, memory devices, and RF modules directly in a cell phone handset, tablet and notebook computer. Emerging complexity with mobile platforms dictates that traditional methods of validating platform performance is not adequate with significant value in the ability to plug packaged IC devices into the actual consumer platform to validate silicon and performance. The paper will document the package substrate to connector interface as well as introduce very high performance connector and flex cable interconnects on 0.35 mm pitch area array for mobile, desktop, and server applications.

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology

Modern mobile processors integrating an increasing number of cores into one single chip demand large-capacity, on-chip, last-level caches (LLCs) in order to achieve scalable performance improvements. However, adopting traditional memory technologies such as SRAM and embedded DRAM (eDRAM) leakage and scalability problems. Spin-transfer torque magnetic RAM (STT-MRAM) is a novel nonvolatile memory technology that has emerged as a promising alternative for constructing on-chip caches in high-end mobile processors. STT-MRAM has many advantages, such as short read latency, zero leakage from the memory cell, and better scalability than eDRAM and SRAM. Multilevel cell (MLC) STT-MRAM further enlarges capacity and reduces per-bit cost by storing more bits in one cell. However, MLC STT-MRAM has long write latency which limits the effectiveness of MLC STT-MRAM-based LLCs. In this article, we address this limitation with three novel designs: line pairing (LP), line swapping (LS), and dynamic LP/LS enabler (DLE). LP forms fast cache lines by reorganizing MLC soft bits which are faster to write. LS dynamically stores frequently-written data into these fast cache lines. We then propose a dynamic LP/LS enabler (DLE) to enable LP and LS only if they help to improve the overall cache performance. Our experimental results show that the proposed designs improve system performance by 9--15% and reduce energy consumption by 14--21% for various types of mobile processors.

Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines

In recent years, dynamic program analysis (DPA) has been widely used in various fields such as profiling, finding bugs, and security. However, existing solutions have their own weaknesses. Software solutions provide flexibility in DPA but they suffer from tremendous performance overhead. In contrast, core-level hardware engines rely on specialized integrated logics and attain extremely fast computation, but they have a limited functional extensibility because the logics are tightly coupled with the host processor. To mend this, a prior system-level approach utilizes an existing channel to integrate their hardware without necessitating the host architecture modification and introduced great potential in performance. Nevertheless, the prior work does not address the detailed design and implementation of the engine, which is quite essential to leverage the deployment on real systems. To address this, in this article, we propose an implementation of programmable DPA hardware engine, called program analysis unit (PAU). PAU is an application-specific instruction-set processor (ASIP) whose instruction set is customized to reflect common features of various DPA methods. With the specialized architecture and programmability of software, our PAU aims at fast computation and sufficient flexibility. In our case studies on several DPA techniques, we show that our ASIP approach can be successfully applicable to complex DPA schemes while providing hardware-backed power in performance and software-based flexibility in analysis. Recent experiments on our FPGA prototype revealed that the performance of PAU is 4.7-13.6 times faster than pure software DPA, and the power/area consumption is also acceptably small compared to today's mobile processors.

On the Impacts of Greedy Thermal Management in Mobile Devices

As mobile system-on-chips incorporate multicore processors with high power densities, high chip temperatures are becoming a rising concern in mobile processors. Modern smartphones are limited in their cooling capabilities and employ CPU throttling mechanisms to avoid thermal emergencies by sacrificing performance. Traditional throttling techniques aim at achieving maximum utilization of the available thermal headroom so as to minimize the performance penalty at a given time. This letter demonstrates that such greedy techniques lead to fast elevation of temperature on other system components and cause substantially suboptimal performance over increased durations of phone activity. Through experiments on a commercial smartphone, we characterize the impact of application duration on throttling-induced performance loss and propose quality-of-service (QoS) tuning as an effective way of providing the mobile system user with consistent performance levels over extended application durations. The proposed QoS-aware frequency capping technique achieves up to 56% improvement in performance sustainability.

Resilient Cache Design for Mobile Processors in the Near-Threshold Regime

Resilient Cache Design for Mobile Processors in the Near-Threshold Regime

Denver: Nvidia's First 64-bit ARM Processor

Nvidia's first 64-bit ARM processor, code-named Denver, leverages a host of new technologies like dynamic code optimization (DCO) to enable high-performance mobile computing. Implemented in a 28-nm process, the Denver CPU can attain clock speeds of up to 2.5 GHz. This article outlines the Denver architecture, describes technological innovations, and provides relevant comparisons against competing mobile processors.

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.