The electrical properties of CdTe and CdMnTe layers grown on (001) InSb substrates by MBE have been studied as a function of depth through the layers. Using capacitance-voltage profiling techniques, the free carrier concentration has been found to be significantly reduced in the vicinity of the substrate and corresponding depth-resolved DLTS measurements have revealed the presence of trapping states only in the region of reduced carrier density. For Cd 1− x Mn xTe layers, a greater reduction in carrier density is observed as the Mn concentration is increased. These observations are explained in terms of the presence of extended defects which are expected to result from the relief of strain due to lattice mismatch at the substrate-epilayer interface. This interpretation is supported by measurements and computer-aided simulations of DCXRD rocking curves which indicate a graded strain structure in these layers.