MNOS Devices Research Articles

ChemInform Abstract: The Combined Effect of Hydrogen and Oxygen Impurities in the Silicon Nitride Film of MNOS Devices

The combined effect of varying the hydrogen and oxygen impurities in the silicon nitride film of metal-nitride-oxide-semiconductor (NOS) devices was studied to develop a correlation among the chemical composition, current conduction, charge trapping, and memory properties of the devices. The atomic percentage of hydrogen increased in the film as a function of decreasing deposition temperature from 850 to 650 o C. Oxygen was incorporated into the film by replacing nitrogen atoms through the use of nitrous oxide gas during the film deposition process. The addition of oxygen further reduced the hydrogen concentration in the fim

ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY

This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge QI is found in MNOS devices with a higher oxide thickness xox. An xox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge QI can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO2/Si3N4 insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.

Estimation of insulation layer conductance in MNOS structure

A method for estimating the conductance of each insulation layer of MNOS devices is described. In this method, the conductance values can be independently estimated using the frequency dependence of the capacitance and conductance versus gate voltage characteristics. The frequency dependence in the accumulation region can be explained by an equivalent circuit which considers the substrate resistance and the conductance of each insulation layer. It was found that the conduction processes in nitride and oxide layers are dominated by Frenkel-Poole emission and direct tunnelling emission, respectively, and that the degradation of retention characteristics of MNOS memory devices with erase/write cycles is caused by increased nitride conductance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interface and Bulk Traps in Oxide-Nitride Stacked Films

ABSTRACTA new technique for the characterization of nitride electron traps responsible for the memory action of MNOS devices is proposed. It is assumed a uniform density of traps in the nitride bulk and an excess of interface traps which is described according to an exponential decreasing distribution. We have modelled the discharge of MNOS devices induced by the application of low positive gate voltages in samples previously charged up toits maximum level of trap occupancy. Since the discharge rate is necessarily dependent on the trapped charge distribution, it is possible to infer the spatial profile of traps by comparing the results obtained by computer simulation of the model to those obtained from field assisted discharge experiences in MNOS samples.

Transient analysis of charge transport in the nitride of MNOS devices under Fowler-Nordheim injection conditions

The transient behavior of current density distributions in the nitride of MNOS devices subjected to constant current stress has been studied via numerical calculation and on the basis of Arnett's trapping model. We have found that under low injection conditions the current distributions can be well described by two parameters which have an easy physical interpretation and the time evolution of which is directly related to the characteristics of the capture centers. A new method to obtain the trapping parameters, based on the measure of the transient of current at the anode of samples with different nitride thickness, is proposed.

Ultrathin stacked Si 3 N 4 /SiO 2 gate dielectrics prepared by rapid thermal processing

Ultrathin (58 Å equivalent oxide thickness) stacked Si3N4/SiO2 (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O2 and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO2 and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flatband voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> write/erase cycles.

Defect States in Silicon Nitride

AbstractThe energy levels of defect centers in amorphous silicon nitride have been calculated. The results are related to recent photoemission and light-induced electron spin resonancedata. The Si dangling bond is argued to be the memory trap in MNOS devices and to be responsible for the electron accumulation at interfaces with amorphous silicon and for the n-type chargetransfer doping of amorphous silicon-silicon nitride superlattices.

A byte erasable 5V‐only 64 kbit EEPROM

AbstractAt present, the main products of high‐performance EEPROMs which can be accommodated in recent high‐speed microcomputers are 16 K bit devices which require two supplies (VCC and VPP). In this paper, a next generation EEPROM which can provide high performance and functionality such as: (1) high density (64 K bit); (2) byte erasable; and (3) internal programming supply is described. The memory device used is a reliable n‐channel Si gate MNOS device.To realize a high density of 64 K, the miniaturization of the MNOS device has been examined, and the scaling law is proposed. Also, to accomplish a reliable byte erasing, a timing is set up for a high‐voltage switching circuit whose current supply capability is designed to have a sufficient margin so that the rate of high‐voltage application into the memory array is determined approximately by the voltage multiplication rate of the multiplier circuit. The generation of high voltage is done by charge pumping method, and a zener diode is used for the stabilization.

Characterization of Oxide‐Nitride Interface Charges in MNOS Devices

Effects of deposition processes on interface charges in MNOS devices have been studied. The deposition of on (400–500Å) introduces fixed positive charges located at interface. The fixed positive charges are introduced during the initial stages of nitride deposition and appear to be localized to a nonstoichiometric region of the order of a couple of hundred angstrom thickness. An anneal at 900°–950°C reduces the density of these positive charges to almost half of the unannealed value.

1/f noise in thin oxide p-channel metal–nitride–oxide–silicon transistors

The 1/f noise behavior of p-channel metal–nitride–oxide–silicon transistors is presented. Devices with different oxide thicknesses, geometries and different technological treatments were used for this study. It is shown that the noise behavior can be well explained quantitatively with the number fluctuation model developed for MOS transistors. The close correlation between the increase of the noise and of the interface state density after different levels of degradation indeed indicates that the exchange of carriers between the channel and the interface traps lies at the origin of the 1/f noise. The observed degradation in MNOS devices is consistent with a diffusion controlled model for the creation of surface traps but is found to be a saturating effect. The predictions of the mobility fluctuation model are not confirmed in our experiments.

A low-voltage alterable EEPROM with metal&amp;#8212;oxide-nitride&amp;#8212;oxide&amp;#8212;semiconductor (MONOS) structures

Theoretical and experimental investigations to obtain lower voltage electrically erasable and programmable ROM's (EEPROM's) than conventional devices have been performed. The scaled-down metal-oxide-nitride-oxide-semiconductor (MONOS) structure is proposed to realize an extremely low-voltage programmable device. The proposed scaled-down MONOS devices enjoy several advantages over MNOS devices, e.g., enlargement of the memory window, elimination of degradation phenomena, and drastic improvement in device yield. Low-voltage operation with ± 6-V supplies is demonstrated by the fabricated scaled-down MONOS transistors.

Composition and electron stress effects in silicon nitride thin films made by thermal growth and chemical etching of LPCVD MNOS structures as studied by x-ray photoelectron spectroscopy (XPS)

XPS has been used in conjunction with stopped-flow chemical etching and angular resolution to obtain depth profies and interface structures of native oxide LPCVD MNOS structures and thermally-grown silicon nitride films. Depth profiling of LPCVD samples required stopped-flow etching with HF/H3PO4/ethanol (15:10:60). A uniform composition of nearly stoichiometric Si3N4 was found throughout the bulk; SiO2 was found intact at the interface along with a sharp Si3N4/SiO2 interface width of 8–10 Å. Another LPCVD sample was etched to ∠30 Å and subjected to a low-energy electron flux in an XPS investigation of degradation mechanisms of MNOS devices; cleavage of Si–H bonds was observed. Angle-resolved XPS on thin, thermally grown films showed a compositional gradient ranging from a high concentration of oxide at the surface to nearly pure Si3N4 at the interface. The results are related to interface state formation and mechanisms of MNOS memory degradation and film growth.

Mnos memory degradation model and its lifetime

AbstractThe large change in the characteristics of MNOS memory results from the variation of the trapping level charge in the interface of SiO2 and SiN with time. Thus, MNOS memory has the drawback of short life. It is difficult to understand the change in the aging characteristics by means of functional tests, but for digital LSI the operation‐limited supply voltage variation method can be used to characterize the variation of intrinsic device characteristics.In this paper the above‐mentioned method is actually applied to the MNOS memory, and a capacitor charging and discharging model is proposed to quantify the aging‐caused changes. The agreement between the test results and the model, the activation energy for the changes, as well as the calculation method for the lifetime are presented.It is shown that the MNOS device change can be estimated by the operation‐limited supply voltage test method, the magnitude of the change in the characteristics due to aging is modeled as an exponential function exp (‐t/τ) with respect to the time t and time constant τ, which can be shortened with an increase in temperature. Its activation energy is found to be 0.2 eV and the life is proportional to τ.

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

Endurance and retention of mnos devices over the temperature range from −50°c to +125°c

The effect of temperature variation on the endurance and retention characteristics of MNOS devices has been studied over the temperature range from −50°c to +125°C. The endurance of MNOS devices is significantly degraded as temperature is increased. Retention, on the other hand, appears to be a more sensitive function of endurance cycling than increased temperature. Increased nitride conductivity, thermal excitation tunneling and charge centroid movement at higher temperatures along with increased surface state density caused by endurance cycling are suggested as mechanisms to explain observed degradation in device performance.

IVB-5 fatigued-induced defects in MNOS devices

IVB-5 fatigued-induced defects in MNOS devices

The effect of ion induced roughness on the depth resolution of Auger sputter profiling of MNOS devices

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