Abstract
AbstractAt present, the main products of high‐performance EEPROMs which can be accommodated in recent high‐speed microcomputers are 16 K bit devices which require two supplies (VCC and VPP). In this paper, a next generation EEPROM which can provide high performance and functionality such as: (1) high density (64 K bit); (2) byte erasable; and (3) internal programming supply is described. The memory device used is a reliable n‐channel Si gate MNOS device.To realize a high density of 64 K, the miniaturization of the MNOS device has been examined, and the scaling law is proposed. Also, to accomplish a reliable byte erasing, a timing is set up for a high‐voltage switching circuit whose current supply capability is designed to have a sufficient margin so that the rate of high‐voltage application into the memory array is determined approximately by the voltage multiplication rate of the multiplier circuit. The generation of high voltage is done by charge pumping method, and a zener diode is used for the stabilization.
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