Μm Thick Buffer Research Articles

750 V Breakdown in GaN Buffer on 200 mm SOI Substrates Using Reverse-Stepped Superlattice Layers

In this work, we demonstrated the epitaxial growth of a gallium nitride (GaN) buffer structure on 200 mm SOI (silicon-on-insulator) substrates. This epitaxial layer is grown using a reversed stepped superlattice buffer (RSSL), which is composed of two superlattice (SL) layers with different Al component ratios stacked in reverse order. The upper layer, with a higher Al component ratio, introduces tensile stress instead of accumulative compressive stress and reduces the in situ curvature of the wafer, thereby achieving a well-controlled wafer bow ≤ ±50 µm for a 3.3 µm thick buffer. Thanks to the compliant SOI substrate, good crystal quality of the grown GaN layers was obtained, and a breakdown voltage of 750 V for a 3.3 µm thick GaN buffer was achieved. The breakdown field strength of the epitaxial GaN buffer layer on the SOI substrate is estimated to be ~2.27 MV/cm, which is higher than the breakdown field strength of the GaN-on-Si epitaxial buffer layer. This RSSL buffer also demonstrated a low buffer dispersion of less than 10%, which is good enough for the further processing of device and circuit fabrication. A D-mode GaN HEMT was fabricated on this RSSL buffer, which showed a good on/off ratio of ~109 and a breakdown voltage of 450 V.

New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (V th) of +0.4 V and +0.9 V respectively with ΔV th about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an I ON/I OFF about 108 and a breakdown voltage of V BR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.

Transformation of the defect structure of InGaAs and InAlAs metamorphic buffer layers depending on indium concentration

A study of samples grown by molecular beam epitaxy using the technology of InxAl1-xAs or InxGa1-xAs metamorphic buffer layer formation on GaAs (001) substrate was performed by transmission electron microscopy. The 1 μm thick buffer layers with square-root dependence of In content on buffer layer thickness were studied in plan-view and cross-section geometries. The results demonstrate cascade step-wise relaxation of misfit strain along buffer layer thickness with the reduction of dislocation density to less than 10−6 cm−2 at the subsurface region. An inhomogeneous distribution of dislocations observed on plan-view TEM images is explained by overlap of split-level dislocation networks with different periods.

Threading Dislocations in InGaAs/GaAs (001) Buffer Layers for Metamorphic High Electron Mobility Transistors

In order to evaluate various buffer layers for metamorphic devices, threading dislocation densities have been calculated for uniform composition In x Ga1−xAs device layers deposited on GaAs (001) substrates with an intermediate graded buffer layer using the LMD model, where LMD is the average length of misfit dislocations. On this basis, we compare the relative effectiveness of buffer layers with linear, exponential, and S-graded compositional profiles. In the case of a 2 μm thick buffer layer linear grading results in higher threading dislocation densities in the device layer compared to either exponential or S-grading. When exponential grading is used, lower threading dislocation densities are obtained with a smaller length constant. In the S-graded case, lower threading dislocation densities result when a smaller standard deviation parameter is used. As the buffer layer thickness is decreased from 2 μm to 0.1 μm all of the above effects are diminished, and the absolute threading dislocation densities increase.

Investigation of Carrot Reduction Effect on 4H-Silicon Carbide Epitaxial Wafers with Optimized Buffer Layer

We investigated the carrot-defect reduction effect by optimizing the buffer layers of 4H-Silion Carbide (SiC) epitaxial wafers. The SiC epitaxial wafer with the 0.5 μm-thick optimized condition-B buffer layer show the carrot-defect density of 0.13 cm-2, since that with the conventional-A buffer layer were 0.68 cm-2. Although the average bunching length with the optimized condition-B buffer layer was 7-times longer than those with the conventional condition-A buffer layer, we could reduce the bunching length by applying the optimized condition-B only to the initial 0.05 μm-thick buffer layer. Finally, with the initial 0.05 μm-thick optimized condition-B buffer layers, we could achieve the SiC epitaxial wafers with only half the carrot-defect densities of those with the conventional condition-A buffer layers, while the average bunching lengths were less than 100 μm. With this condition, we could achieve the estimated yield of 90.1% with 4 x 4 mm chips, while that with the conventional condition-A buffer layer was 81.9%.

Influence of metal-organic vapor phase epitaxy parameters and Si(111) substrate type on the properties of AlGaN/GaN HEMTs with thin simple buffer

The present work is dedicated to the study of the influence of metal-organic vapor phase epitaxy (MOVPE) growth conditions on the properties of AlGaN/GaN high electron mobility transistor (HEMT) heterostructures with thin simple buffer layers on Si(111). In a first series of samples grown on high resistivity silicon, the conditions were varied within the GaN buffer layer while kept unchanged for the AlN nucleation layer and HEMT barrier and cap layers. XRD and AFM revealed some differences in epilayers structural quality especially in case of excessive growth pressure or V/III ratio. Capacitance–voltage (CV) measurements revealed differences in the pinch-off regime of the two-dimensional electron gas (2DEG) located at the AlN/GaN interface. Except in one case, the buffer leakage current between isolated devices correlates with the pinch-off behavior. The majority of these structures exhibited sheet carrier densities of 1 × 1013 cm−2 and electron mobility between 1100 and 1400 cm2 V −1 s−1 depending on the GaN channel growth conditions. The output and transfer characteristics (maximum drain currents and leakage currents) of the transistors are in agreement with the previous electrical characterizations. Thanks to the combination of structural and electrical characterizations we are then able to determine the optimized growth conditions for such HEMT structures. Compared with high resistivity silicon, we obtained better structural and electrical quality on conductive substrates. A 2DEG with an electron mobility of 1700 cm2 V−1 s−1 has been achieved within a structure with a 0.5 μm thick buffer producing an off-state breakdown voltage of 117 V. This reveals the crucial role of the substrate surface properties on the resulting quality of the heterostructures.

Heteroepitaxial growth of In0.30Ga0.70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm−2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with IDS of 70 μA/μm and gm of above 60 μS/μm, demonstrating the high quality of the grown materials.

Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode With Gated Edge Termination on 200-mm Silicon Substrate

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver ~4 A at 2 V and show a median leakage of 1.3 μA at 25 °C and 3.8 μA at 150 °C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of ~600 V for the GET-SBDs with LAC larger than 5 μm. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 μm-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 μm) and remains at a value of ~10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.

Co-Electrolysis Cell Configurations for CO2 Electrochemical Reduction

Although the electrochemical reduction of CO2 has been extensively studied over the past decades, with a renewed interest in the past 5 years, this topic has been tackled so far only by using a very fundamental approach, i.e., mostly by trying to understand and improve faradaic efficiencies, kinetics and selectivities toward certain products in half cell configurations and liquid based electrolytes (such as KHCO3) (1). The main drawback of this approach is that, due to the low solubility of CO2 in water, the maximum current which could be drawn falls in the range of 10-20 mA/cm2 even under the most optimized convection conditions. In this work, CO2 is intended to be electrochemically reduced in a co-electrolysis system, i.e., a device similar to a water electrolyzer where the hydrogen evolving cathode is substituted by a CO2 reduction one. By making the analogy with state-of-the-art water alkaline electrolyzers, such co-electrolysis system starts to be interesting from an energy efficiency point of view only if large currents (>100 mA/cm2) can be drawn from the anodic and cathodic electrochemical reactions (2). Due to the additional difficulty to prepare heavy metal impurity free pure liquid carbonate based electrolytes (below the ppm level to avoid cathodic metal plating and facilitated hydrogen evolution), the motivation is the development of a membrane-based cell using liquid electrolyte free gas diffusion electrodes for the CO2 reduction reaction. This strategy is proven to enable operation at cell current densities > 1 A/cm2 in Proton Exchange Membrane (PEM)-electrolyzer and Polymer Electrolyte Fuel Cells. Only very few reports have already investigated the use of gas diffusion electrodes for the CO2 reduction reaction (3, 4). In what we identified as the most promising co-electrolysis approach, unsupported gold or silver assembled in the CO2 reduction electrode were separated from the oxygen evolution electrode through an 800 µm thick buffer layer filled with a 0.5 M KHCO3 solution and a 50 µm thick cation exchange membrane (3, 4). These were the first experimental reports showing that CO2 reduction currents of ≈140 mA/cm2 for forming CO could be achieved at an overpotential of ≈0.5 V. Nevertheless, in this cell configuration, the CO2 reduction electrode is in contact with a buffer layer consisting of a concentrated KHCO3 solution, and therefore the question whether such configuration could sustain high CO2 reduction currents over time due to contamination issues is questionable. In this contribution, we will report alternative liquid electrolyte free cell configurations for co-electrolysis operation. The most promising configurations will be characterized using a small scale electrolysis cell (1cm2 active area), and the CO2 reaction products will be analyzed by using an on line mass spectrometer (MS) coupled to the gas outlet of the electrolysis cell. Since only gaseous products can be detect by MS, unsupported Cu and Au nanoparticles which produce mostly CH4/C2H4 and CO species respectively will be used as catalysts in the CO2 reduction electrode.

High-efficiency and wideband interlayer grating couplers in multilayer Si/SiO2/SiN platform for 3D integration of optical functionalities.

We have designed interlayer grating couplers with single/double metallic reflectors for Si/SiO(2)/SiN multilayer material platform. Out-of-plane diffractive grating couplers separated by 1.6 μm thick buffer SiO(2) layer are vertically stacked against each other in Si and SiN layers. Geometrical optimization using genetic algorithm coupled with electromagnetic simulations using two-dimensional (2D) finite element method (FEM) results in coupler designs with high peak coupling efficiency of up to 89% for double- mirror and 64% for single-mirror structures at telecom wavelength. Also, 3-dB bandwidths of 40 nm and 50 nm are theoretically predicted for the two designs, respectively. We have fabricated the grating coupler structure with single mirror. Measured values for insertion loss and 3-dB bandwidth in the fabricated single-mirror coupler confirms the theoretical results. This opens up the possibility of low-loss 3D dense integration of optical functionalities in hybrid material platforms.

The Influence of Superlattice on the Internal Quantum Efficiency of LED Structures with InGaN / GaN Quantum Wells

epitaxy. The structures were grown on the planar and profiled sapphire substrates with the (0001) orientation. Two groups of samples were investigated. The LED-structures of the group QB were grown on the planar sapphire substrates and were composed of a low-temperature nucleation layer, a 2 µm-thick buffer i-GaN layer, a 2 µm-thick n-GaN layer, an active region consisting of 5 InGaN quantum wells with the thickness 2.5–3 nm and GaN barrier layers with the thickness 3–15 nm (an InN content in the InхGa1–хN solid solution was 10–15%), and a 140 nm-thick p-GaN layer. In addition, in the buffer region of some samples of the group QB, a short-period InGaN / GaN superlattice with the 1 nmthick layers was grown. The samples of the LQB group grown on the planar and profiled sapphire substrates consisted of a low-temperature nucleation layer, a 4 µm-thick buffer i-GaN layer, a 2 µm-thick n-GaN layer, an active region consisting of 10 InGaN quantum wells with the thickness 3 nm and GaN barrier layers with the thickness 15 nm, and a 140 nm-thick p-GaN layer. In the samples of the LQB group, the thickness of the last barrier GaN layer, located between the active region and the p-GaN layer, varied in the range 5–15 nm. The grown samples were studied by the methods of electro- and photoluminescence. For the electroluminescence (EL) measurements, indium contacts were fused into the samples. The measurements were carried out at room temperature at low currents (up to 5mA) in a pulsed mode. The external quantum efficiency (EQE) was estimated from the slope of the photodetector current–current through the sample dependence. Photoluminescence (PL) spectra were measured in the temperature range 10–300 K using an optical cryostat. A pulsed YAG-laser with an average power of 35 mW (1 kHz, pulse duration – 10 ns, wavelength – 355 nm) was used as an excitation source. To determine the internal quantum efficiency (IQE), an integrated PL intensity was measured as a function of the excitation radiation intensity [3, 4].

Strain control of AlGaN/GaN high electron mobility transistor structures on silicon (111) by plasma assisted molecular beam epitaxy

This paper reports on the use of plasma assisted molecular beam epitaxy of AlGaN/GaN-based high electron mobility transistor structures grown on 4 in. Si (111) substrates. In situ measurements of wafer curvature during growth proved to be a very powerful method to analyze the buffer layer’s thickness dependent strain. The Ga/N ratio at the beginning of growth of the GaN buffer layer is the critical parameter to control the compressive strain of the entire grown structure. An engineered amount of compressive strain must be designed into the structure to perfectly compensate for the tensile strain caused by differences in the thermal expansion coefficient between the epi-layer and substrate during sample cool down from growth temperatures. A maximum film thickness of 4.2 μm was achieved without the formation of any cracks and a negligible bow of the wafers below 10 μm. Measurement of the as-grown wafers revealed depth profiles of the charge carrier concentration comparable to values achieved on SiC substrates and mobility values of the two dimensional electron gas in the range 1230 to 1350 cm2/Vs at a charge carrier concentration of 6.5–7 1012/cm2. First results on processed wafers with 2 μm thick buffer layer indicate very promising results with a resistance of the buffer, measured on 200 μm long contacts with 15 μm pitch, in the range of R > 109 Ω at 100 V and breakdown voltages up to 550 V.

High vertical breakdown strength in with low specific on‐resistance AlGaN/AlN/GaN HEMTs on silicon

AbstractOff‐state and vertical breakdown characteristics of AlGaN/AlN/GaN high‐electron‐mobility transistors (HEMTs) on high‐resistivity (HR)‐Si substrate were investigated and analysed. Three‐terminal off‐state breakdown (BVgd) was measured as a function of gate–drain spacing (Lgd). The saturation of BVgd with Lgd is because of increased gate leakage current. HEMTs with Lgd = 6 µm exhibited a specific on‐resistance RDS[ON] of 0.45 mΩ cm2. The figure of merit (FOM = BVgd2/RDS[ON]) is as high as 2.0 × 108 V2 Ω–1 cm–2, the highest among the reported values for GaN HEMTs on Si substrate. A vertical breakdown of ∼1000 V was observed on 1.2 µm thick buffer GaN/AlN grown on Si substrate. The occurrence of high breakdown voltage is due to the high quality of GaN/AlN buffer layers on Si substrate with reduced threading dislocations which has been confirmed by transmission electron microscopy (TEM). This indicates that the AlGaN/AlN/GaN HEMT with 1.2 µm thick GaN/AlN buffer on Si substrate is promising candidate for high‐power and high‐speed switching device applications. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Well-Aligned Ternary Cd1-xZnxS Nanowire Arrays and Their Composition-Dependent Field Emission Properties

Well-aligned plain CdS and ternary Cd1-xZnxS nanowire arrays were successfully fabricated via a noncatalytic and template-free metal−organic chemical vapor deposition process. The nanowires were grown on a 1 μm thick buffer layer formed in situ on the surface of silicon substrates. These nanowires were 20−40 nm in diameter and 500−900 nm in length. High-resolution transmission electron microscopy analyses revealed that the nanowires were single-crystalline and grew along the [0001] direction of the hexagonal crystalline phase. The photoluminescence characterizations showed near band edge emissions at 535, 498, and 473 nm for the CdS nanowire arrays and Cd1-xZnxS nanowire arrays with x values of 0.21 and 0.44, respectively, demonstrating clear color tunability achieved with the composition adjustment of the alloy nanowires. The same morphology and single-crystallinity of these three nanowire arrays enabled investigation of the composition-dependent field emission characteristics of the nanowire arrays for the first time, excluding interferences originating from morphology and crystallinity related factors. The plain CdS nanowire arrays exhibited better field emission properties, a lower turn-on field, and a higher field enhancement factor than the ternary Cd1-xZnxS nanowire arrays, for which the lower resistivity of the CdS nanowires may have played an important role. An important parameter, the absolute field enhancement factor (β0), to more intrinsically quantify the field emission performance of the plain CdS and ternary Cd1-xZnxS nanowires arrays was also studied. The values of β0 decreased with increasing Zn content in the ternary products. The high β0 values of the CdS based nanowire arrays, comparable to that of carbon nanotubes grown on silicon wafers, made these nanowire arrays a promising candidate material for high-performance field emitting devices.

Development of 6.00Å graded metamorphic buffer layers and high performance In0.86Al0.14As∕In0.86Ga0.14As heterojunction bipolar transistor devices

In x Al 1 − x As ∕ In x Ga 1 − x As heterojunction bipolar transistors (HBTs) with lattice parameters ranging from 6.00to6.058Å employing the use of narrow band gap InxGa1−xAs base epitaxial layers toward InAs (0.86<Xln<1) allows for the development of high speed digital and mixed signal circuits to perform at half the power required for conventional group III-V-based HBT device technologies. However, one of the key challenges inhibiting the development of low power narrow band gap HBT device circuits is the absence of semi-insulating (SI) substrates with lattice parameters towards 6.058Å. Therefore, a metamorphic InxAl1−xAs (0.52<Xln<0.86) graded buffer layer (GBL) grown on InP by molecular beam epitaxy was investigated as a means to enable a SI template with a lattice parameter of 6.00Å. The metamorphic InxAl1−xAs GBL thickness is desired to be less than a micron in order for this approach to be compatible with the aggressive design rules of high-density transistor circuits. In this study, In0.86Al0.14As∕In0.86Ga0.14As double heterojunction bipolar transistor devices were grown on 0.90, 0.45, and 0.23μm thick InxAl1−xAs GBLs to assess the role of buffer layer thickness on both defect formation and device performance. The material characterization results for the 0.90 and 0.45μm thick buffer layers exhibited a crosshatch pattern with a surface rms roughness of 4nm and threading dislocation densities of ∼106cm−2. Excellent dc and rf characteristics from metamorphic HBT devices with submicron emitter widths were observed with low turn-on voltage of 0.45V, high current gain, low reverse junction leakage(<1μA), and rf peak performance in the vicinity of 150GHz. Finally, preliminary circuits (dividers and delay chains) have been designed, fabricated, and demonstrated with the 6.00Å HBT technology.

Microstructural Characterization of Au-Ge-Ni based ohmic contacts to GaAs/AlGaAs modfet device

Considerable amount of work has been done in studying the relationship between the contact resistance and the microstructure of the Au-Ge-Ni based ohmic contacts to n-GaAs. It has been found that the lower contact resistivity is due to the presence of Ge rich and Au free regions (good contact area) in contact with GaAs. Thus in order to obtain an ohmic contact with lower contact resistance one should obtain a uniformly alloyed region of good contact areas almost everywhere. This can possibly be accomplished by utilizing various alloying schemes. In this work microstructural characterization, employing TEM techniques, of the sequentially deposited Au-Ge-Ni based ohmic contact to the MODFET device is presented.The substrate used in the present work consists of 1 μm thick buffer layer of GaAs grown on a semi-insulating GaAs substrate followed by a 25 Å spacer layer of undoped AlGaAs.

Molecular beam epitaxial growth and characterization of lead telluride for laser diodes

The characteristics of PbTe films grown by molecular beam epitaxy (MBE) have been investigated. These films were grown on (100) oriented Tl-doped PbTe substrates under UHV conditions (~5×l0−9 Torr during deposition). Substrate surface contamination levels were studied with Auger electron spectroscopy. Oxygen, the dominant impurity observed, is rapidly thermally desorbed from PbTe, but is stable on Pb1−xSnxTe up to at least 410°C. Carrier concentration and mobility were measured with the Van der Pauw technique. The electron mobility increased strongly with increasing film thickness, varying from 4,000 to 14,000 cm2/volt-sec as the thickness increased from 2.0 to 7.3 µn. The film surface also became smoother with increasing film thickness. These results suggest the need for a buffer layer in a laser structure. Lasers grown with 6 μm thick buffer layers have exhibited extremely low threshold current densities (40 A/cm2 at 13 K) and very high junction resistancearea products at zero-bias (0.7 Ω−cm2 at 77 K), indicative of very high junction quality.