Μm Technology Research Articles

INLEC: An involutive and low energy lightweight block cipher for internet of things

The Internet of Things (IoT) has emerged as a pivotal force in the global technological revolution and industrial transformation.Despite its advancements, IoT devices continue to face significant security challenges, particularly during data transmission, and are often constrained by limited battery life and energy resources.To address these challenges,a low energy lightweight block cipher (INLEC) is proposed to mitigate data leakage in IoT devices. In addition, the Structure and Components INvolution (SCIN) design is introduced. It is constructed using two similar round functions to achieve front–back symmetry.This design ensures coherence throughout the INLEC encryption and decryption processes and addresses the increased resource consumption during the decryption phase in Substitution Permutation Networks (SPN).Furthermore, a low area S-box is generated through a hardware gate-level circuit search method combined with Genetic Programming (GP).This optimization leads to a 47.02% reduction in area compared to the S0 of Midori, using UMC 0.18μm technology. Moreover, a chaotic function is used to generate the optimal nibble-based involutive permutation, further enhancing its efficiency.In terms of performs, the energy consumption for both encryption and decryption with INLEC is 6.88 μJ/bit, representing 25.21% reduction compared to Midori.Finally, INLEC is implemented using STM32L475 PanDuoLa and Nexys A7 FPGA development boards, establishing an encryption platform for IoT devices. This platform provides functions for data acquisition, transmission, and encryption.

A voltage-mode fully cascadable biquad with three CFOAs and grounded capacitors

In this paper, a new voltage-mode second-order multifunction filter with three current feedback operational amplifiers is developed. This circuit generates low-pass filter, band-pass filter (BPF), inverting-type BPF, notch filter, and all-pass filter (APF) responses with all gains. It has high input and low output impedances for all the filter responses. It also has the advantage of grounded two capacitors, which is essential for integrated circuit technology. It has orthogonally controllable features for all the filter responses except the APF one. However, one passive element matching condition is needed to obtain an APF response. Many simulations are carried out via the SPICE program, where 0.13 µm technology parameters are utilized. Furthermore, a few experiments are performed using the AD844s to see the performance of the developed filter in practice.

A high-gain high-drive operational amplifier

Abstract This paper presents a high-gain, high-drive operational amplifier based on the 0.18 μm technology. The first stage employs a current-reuse common-source common-gate structure to enhance gain, while the second stage utilizes a transconductance-enhanced push-pull output stage. This design achieves high-drive performance while retaining a high gain. Simulation using Cadence software demonstrates that, under a 5 V power supply voltage, the amplifier exhibits a low-frequency gain of 120 dB, with output sink and source current capabilities reaching 17.7 mA and 2.53 mA, respectively.

A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog Converter Based on a High-Linearity Resistor String Poly-Matrix

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.

A novel small-signal equivalent circuit model for GaN HEMTs incorporating a dual-field-plate

An accurate and novel small-signal equivalent circuit model for GaN high-electron-mobility transistors (HEMTs) is proposed, which considers a dual-field-plate (FP) made up of a gate-FP and a source-FP. The equivalent circuit of the overall model is composed of parasitic elements, intrinsic transistors, gate-FP, and source-FP networks. The equivalent circuit of the gate-FP is identical to that of the intrinsic transistor. In order to simplify the complexity of the model, a series combination of a resistor and a capacitor is employed to represent the source-FP. The analytical extraction procedure of the model parameters is presented based on the proposed equivalent circuit. The verification is carried out on a 4 × 250 μm GaN HEMT device with a gate-FP and a source-FP in a 0.45 μm technology. Compared with the classic model, the proposed novel small-signal model shows closer agreement with measured S-parameters in the range of 1.0 to 18.0 GHz.

Two HVCMOS active pixel ASIC designs for the Measurement of GCR and SEP with a combined dynamic range of >80 dB

The design of HVCMOS detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) is presented, with the goal of covering a very wide dynamic range (from ∼0.5 fC to pC). Two different pixel designs are shown, one with low gain tailored to high energy depositions and one with high gain for low energy depositions. Both designs utilize a sensing diode consisting of a fully-depleted, high resistivity substrate and a segmented deep n-well on top. LFoundry 0.15 μm technology is used. The design choices are backed by simulation results and preliminary measurements.

Comparative Study and Design of High Performance Mixer

In recent time the use of RF mixer has been increased greatly. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. Since, CMOS technology has become dominant because of its several advantages such as low cost, low static power dissipation and low area, the design of low noise amplifier using CMOS technology was top choice for design of Low Noise Amplifier. The single ended and differential LNA was designed to operate in a WCDMA reception range using a BSIM3V2 model (Level 49) CMOS UMC 0.18μm technology in Xcircuit Open source EDA tool. The key issues in the design, gain, noise and linearity were considered. The LNA’s was designed to provide high gain, matching to 50Ω RF system, good linearity.

Low Noise Operational Amplifier using Current Driving Bulk by CMOS Technology

A reverse substrate bias operational amplifier using existing driver technology has been designed and implemented using 0.25μm CMOS process to achieve high noise performance. Op amps are efficient and versatile devices. Its applications include signal conditioning, custom conversion, analog equipment, competitive simulation, and various electronic industries meeting custom design requirements. As the trend of low voltage devices continues, designing high-performance analog circuits becomes increasingly difficult. The main module of analog circuits is the work amplifier. In large electronic devices, there is a trade-off between speed, power, and gain, among other drawbacks. Additionally, in order to reduce costs and integrate analog and digital circuits on a single die, analog designers must face the challenges of using the CMOS process. Design and implementation are done in 0.25μm technology using TSMC libraries and with the help of Tanner tools.

Characterization of the electrical properties of an optical device manufactured with CMOS 0.35 μm technology

<p>Currently, the relevance of optical devices has increased due to the physical limitations of the electrical transmission medium and the proximity of the limit of Moore's Law. Furthermore, the fabrication of optical devices on monolithic silicon substrates has gained importance in recent years thanks to manufacturing technologies in the microelectronics industry. For this reason, this paper aims to carry out the electrical characterization of an optical device manufactured with commercial austria micro syste m technology of complementary metal oxide semiconductors of 0.35 μm. The methodology consists of implementing an optical device, with an incandescent optical source called a microlamp, a waveguide and a photodiode. The microlamp was projected between two m etal layers connected by tungsten vias that act as filaments covered by SiO 2 dielectric to prevent oxidation. The results of the electrical characterization of the optical device show that the microlamp reaches a maximum current of 48 mA and stops working at higher currents. The waveguide was designed with a SiO 2 core and it was discovered that the TiN layers were found to be part of the waveguide causing it to behave as an emitter in the 2.5 - 5 <em>µ</em>m region.</p>

A Hybrid CMOS Digital-to-Analogue Converters Design for High Resolution SAR ADC

The paper describes the design and implementation of a 14-bit differential Digital-to-Analogue Converter (DAC) based on the Silterra 0.18µm Complementary Metal-Oxide-Semiconductor (CMOS) process to be established in a Successive Approximation Register (SAR) Analogue-to-Digital Converter (ADC) for the purpose of high-resolution, high accuracy and low power applications. The proposed differential DAC aims to eliminate the issue of stringent matching requirements imposed on high-resolution DACs while leveraging both linearity performance and power consumption parameters at a balanced point. The overall differential circuit consists of two parallel single-ended DACs that utilize a 4-bit Capacitor DAC (CDAC) and 10-bit Resistor DAC (RDAC) on each end, thereby establishing a hybrid-based architecture. Furthermore, the authors illustrate the proposed switching procedures applied to the sub-DAC circuits to ensure a low-power design is established. The new method effectiveness evaluation is confirmed by detailed transient simulations implemented on the DAC where the circuit performs the required conversions at a maximum conversion frequency of 2.5 MS/s with a peak power consumption of 0.1496mW for the standard voltage supply of 2.1V. Meanwhile, the schematic and post-layout simulations performed on the DAC registers peak DNL errors of -0.1612 and -0.8272, respectively. New research results depict performance improvements in terms of resolution and power consumption which facilitates the DAC implementation in contemporary electronic devices such as microcontroller peripherals and audio amplification devices. The overall deigned circuit is capable of achieving the desired 14-bit digital-to-analogue conversions under the CMOS 0.18µm technology, proving the DAC’s high-resolution efficacy.

A 34.7 µW Speech Keyword Spotting IC Based on Subband Energy Feature Extraction

In the era of the Internet of Things (IoT), voice control has enhanced human–machine interaction and the accuracy of keyword spotting (KWS) algorithms has reached 97%; however, the high power consumption of KWS algorithms caused by their huge computing and storage requirements has limited their application in Artificial Intelligence of Things (AIoT) devices. In this study, voice features are extracted by utilizing the fast discrete cosine transform (FDCT) for frequency-domain transformation and to shorten the process of calculating the logarithmic spectrum and cepstrum. The designed KWS system is a two-stage wake-up system, with a sound detection (SD) awakening KWS. The inference process of the KWS network is achieved using time-division computation, reducing the KWS clock to an ultra-low frequency of 24 kHz.At the same time, the implementation of a depthwise separable convolution neural network (DSCNN) greatly reduces the parameter quantity and computation. Under the GSMC 0.11 µm technology, post-layout simulation results show that the total synthesized area of the entire system circuit is 0.58 mm2, the power consumption is 34.7 µW, and the F1-score of the KWS is 0.89 with 10 dB noise, which makes it suitable as a KWS system in AIoT devices.

A Compact Fully Electronically Tunable Memristive Circuit Based on CCCDTA with Experimental Results.

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator's invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features.

Improving the accuracy for amplitude and frequency of analytical equation of single-ended ring oscillators based on circuit and transistor parameters

PurposeThis paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.Design/methodology/approachIn this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.FindingsIn the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.Originality/valueThe validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

Efficient Modulo Multiplier

The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities

In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

28 GHz compact 4‐way Wilkinson power divider/combiner using RCIN and mutual inductors in 0.13 μm CMOS technology

AbstractIn this study, we proposed a 4‐way Wilkinson power divider/combiner (WPDC) with a series RC(resistor‐capacitor) isolation network (RCIN) and mutual inductors for millimeter wave phased array applications. The proposed circuit offers small chip sizes and low insertion loss, measuring less than 0.85 dB, as well as an input/output return loss greater than 11.8 dB. Additionally, simulations showed isolation greater than 18.7 dB, amplitude imbalance less than 0.026 dB, and phase difference less than 0.26° in the 26–32 GHz. The 4‐way WPDC was implemented using bulk CMOS 1P8M 0.13 μm technology and had a circuit size of 0.087 mm².

A Comparative Study of CMOS Transimpedance Amplifier (TIA)

In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters of transimpedance amplifier such as gain, input refereed noise, power dissipation and group delay are studied and compared. Here the transimpedance amplifier is divided on the basis of its topology and device technology used and performance is summarized to get the overview. Most of the analysis taken are performed on 0.18 μm technology and some are implemented using 45nm, 0.13μm, 65nm, and 90nm.

Comparative Single Photon Time Resolution Measurements of Commercial Silicon-Photomultipliers and a Specially Designed SiPM with High Accuracy in 0.35 µm Technology

In this study, we present highly accurate single photon time resolution (SPTR) measurements of proved commercial Silicon-Photomultiplier (SiPM) from Broadcom (AFBR-S4N44C013), KETEK (PM3350), OnSemi (FJ30035) and Hamamatsu (S13360-3050V) with similar dimensions for highly precise SPTR measurements. The principal objective of this project was to investigate the timing precision of SiPM, since they play a key role for users in application areas like time of flight positron emission tomography (TOF-PED). For the SPTR comparative measurements in this research, we used a high-precision measurement setup including a femtosecond laser (λ = 400 nm, pulse width = 70 fs) and an oscilloscope with a 10 GHz bandwidth and a sampling rate of 50 GS/s to keep the influence of the measurement setup on the SPTR as small as possible, so that we are able to measure the true SPTR of commercial SiPM. In order to filter out external noise, we present an offline analysis to get as close as possible to the intrinsic SPTR of each SiPM. Furthermore, this study presents a special designed 4 x 4 SiPM integrated into a 0.35 µm CMOS process. The CMOS SiPM consists of a moderately selected diode capacitance combined with a low grid capacitance leading to very short pulses with a peak width below 2 ns and a peak height of 30 mV at an excess bias voltage of 8 V, facilitating the acquisition without the requirement of a pre-amplifier. The final obtained SPTR results of the commercial SiPM showed values between 191 ps to 104 ps. For the 4 x 4 CMOS SiPM a SPTR of 40 ps was achieved. We also show that SPTR values can be improved by filtering out external noise by a subsequent offline analysis up to 55.5%.

Improving the Accuracy for Amplitude and Frequency of Analytical Equation of Single-ended Ring Oscillators Based on Circuit and Transistor Parameters

The analytical relationships presented for amplitude and frequency of the ring oscillator are derived approximately due to the nonlinear nature of this oscillator. In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. In this paper, considering the circuit’s governing equation and the ring oscillator’s output waveform, a relation for the frequency is presented, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case. The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18μm technology.