Μm BiCMOS Technology Research Articles

A 4.65 [formula omitted]V/V line regulation, transient enhanced, capacitor-less LDO with ultra-low load current dependence

A capacitor-less low-dropout regulator (CL-LDO) based on an improved flipped voltage follower (FVF) cell with robust regulation capability and high transient response is presented. The line regulation (LNR) and load regulation (LAR) are enhanced by a stable DC operating point design and multiple feedback loops. A nested feed-forward gm-stage and a nulling resistor in the nested Miller compensation (NGRNMC) topology ensures stability in various challenging conditions. The proposed CL-LDO was designed in 0.18μm BiCMOS technology and occupied an area of 0.0582 mm2, with a typical input voltage range of 3.0 V–3.6 V and a load range of 0–100 mA. Post-simulation verification under various process, voltage, and temperature (PVT) conditions confirms the design’s robustness and reliability. The proposed design achieves the best figure of merit (FoM) of 1.69 mV among state-of-the-art designs, accompanied by a LNR of 4.65 μV/V and a LAR of 27.881 nV/mA.

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)B, 19 dB (+ 5 dB)B and 45% (+ 5% to 10%)B, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a 732×605 μm2 chip’s surface. (B: indicates the improved values in the power back-off region).

Pulse shape discrimination for GRIT: Beam test of a new integrated charge and current preamplifier coupled with high granularity Silicon detectors

The GRIT (Granularity, Resolution, Identification, Transparency) Silicon array is intended to measure direct reactions. Its design is based on several layers (three layers in the forward direction, two backward) of custom-made trapezoidal and square detectors. The first stage is 500 μm thick and features 128 × 128 orthogonal strips. Pulse shape analysis for particle identification is implemented for this first layer. Given the compacity of this array and the large number of channels involved (>7500), an integrated preamplifier, iPACI, that gives charge and current information has been developed in the AMS 0.35 μm BiCMOS technology. The design specifications and results of the test bench are presented. Considering an energy range of 50 MeV and an energy resolution (FWHM) of 12 keV (FWHM) for the preamplifier, the energy resolution for one strip obtained from alpha source measurement in real conditions is 35 keV. The current output bandwidth is measured at 130 MHz for small signals and the power consumption reaches 40 mW per detector channel. A first beam test was performed coupling a nTD trapezoidal double-sided stripped Silicon detector of GRIT with the iPACI preamplifier and a 64-channel digitizer. Z = 1 particles are discriminated with pulse shape analysis technique down to 2 MeV for protons, 2.5 MeV for deuterons and 3 MeV for tritons. The effect of the strip length due to the trapezoidal shape of the detector is investigated on both the N- and the P-side, showing no significant impact.

A Low Noise 28Gbaud/s Linear PAM4 Receiver Front-End for Optical Communication Applications in 0.13μm BiCMOS Technology

This paper presents a low noise 28 Gbaud/s linear receiver front-end for fourth-order pulse amplitude modulation (PAM4) signal applied in the field of optical communication. The designed receiver front-end includes a transimpedance amplifier(TIA), an automatic gain control (AGC) and a DC offset cancellation (DCOC) circuit. The pseudo-differential structure of the TIA is designed to achieve low noise. The resistance and capacitance degradation technology are introduced in the variable gain amplifier(VGA) and the equalizer(EQ) to improve linearity and optimize the bandwidth. In the AGC mode, the feedback loop controls the output amplitude to be a desired value within a large range of input current. The PAM4 optical receiver front-end achieves a maximum differential transimpedance gain of 76 dBΩ and -3dB bandwidth of 27 GHz. The equivalent input noise current density with the front-end circuit is . In 0.13µm BiCMOS technology, the PAM4 front-end chip consumes 200 mW with a 3.3V voltage supply.

Modeling and experimental evaluation of pseudo-resistor’s temperature dependence

This work presents the experimental temperature dependence evaluation of the pseudo-resistor piecewise linear (PWL) macromodel, for temperature ranging from 300 to 333 K. The studied macromodel is based on the PWL methodology and it can be used for pseudo-resistors SPICE simulation, including both linear and non-linear operation regions. This study was carried out using a low-frequency bio-potential amplifier with narrow bandwidth for use in QRS complex (part of the electrocardiogram which is a combination of the Q wave, R wave and S wave) detection systems. The architecture based on pseudo-resistors provides DC offset cancellation, adequate frequency response and a significant reduction of the signal recovery time. Both the pseudo-resistor and the QRS complex detector performance were experimentally measured with the temperature variation, in order to include this dependency in the PWL model. The transient recovery time, as well as the QRS complex detector frequency response, was also widely evaluated, in the proposed temperature range, through experimental measurements. The temperature dependence was added to the model and implemented in the SPICE simulation. The model outputs showed strong adherence to experimental data, showing a disagreement less than 6% in the low cut-off frequency. The macromodel’s response to the recovery time also followed the same experimental results behavior, presenting a maximum error of 20% within human body temperature range. The obtained recovery time was less than a normal heartbeat period to the entire temperature range evaluated. All of the analyzed circuits were implemented using GF 8HP 0.13 μm BiCMOS technology from Global Foundries.

VLC Using 800-μm Diameter APD Receiver Integrated in Standard 0.35-μm BiCMOS Technology

The fully integrated 800 μm. diameter avalanche photodiode optical receiver is implemented in 0.35 μm BiCMOS technology without any process modifications. The integrated receiver reaches sensitivities of -33 dBm at 1 Gbit/s and -29.3 dBm at 2 Gbit/s. The reached sensitivities are well within the state-of-the-art of integrated avalanche photodiode receivers and can even be compared to a hybrid avalanche photodiode receiver comprised of high-performing commercial components. The performance of the designed receiver was verified in visible light communication experiments. The receiver could reach up to 16.5 m at 2 Gbit/s and 27 m at 1 Gbit/s of error free transmission distance using a 675-nm point laser source as transmitter. The common indoor illuminance levels up to 500 lux could be tolerated when pointed directly towards the receiver. High sensitivity and high speed make this integrated receiver suitable for future optical wireless communication systems, where due to its integrated nature the manufacturing cost can be lowered, and at the same time the design is compact in size and easy to assemble and scale. Furthermore, no optics is used in front of the receiver due to its large area resulting in a wide field of view.

A unified aging compact model for hot carrier degradation under mixed-mode and reverse E-B stress in complementary SiGe HBTs

This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction–diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions. The model accuracy has been validated against results from long-term aging tests performed close to the safe-operating-areas of an advanced complementary 0.25 µm BiCMOS technology. Degradation asymmetry observed between NPN and PNP devices is accurately captured by this unified aging compact model. This study highlights the challenges of predicting degradation of complementary circuits and thereby improving its functionalities by designing better-matched NPN and PNP HBTs.

Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.

Non-linear model for pseudo CMOS resistors addressing the recovery time in bio-amplifiers

This work presents a new fast model, based on piecewise linear (PWL) methodology, for pseudo-resistors SPICE simulation, including the non-linear working range, fully supported by experimental data. SPICE simulations with fixed resistances or transistor modelled as pseudo-resistors do not reproduce simultaneously its real behavior for both the linear and the non-linear regions. A complete set of steps which validate the PWL macromodel for bio-amplifiers project is presented. As a case study, this paper addresses the pseudo-resistor characteristics operating in the non-linear region when implemented in a low-frequency bio-potential amplifier with narrow bandwidth, for use in heart rate meters and QRS complex monitoring systems. The use of the pseudo-resistor in this low-voltage low-power topology associates DC offset cancellation with an adequate frequency response. Moreover, this work shows that the non-linear characteristics of these devices can be used for a significant reduction in bio-amplifier recovery time (a.k.a. settling time) without any additional device or mechanism, making the heart rate measurements steadier and more reliable than obtained so far in current systems. The transient recovery time, as well as the response to QRS complex, was widely evaluated through experimental measurements and SPICE simulations, thanks to the proposed model. The bio-potential amplifier design was implemented using GF 8HP 0.13 μm BiCMOS technology from Global Foundries.

A custom 70-channel mixed signal ASIC for the brain-PET detectors signal readout and selection

This paper presents a 70-channel mixed signal Application Specific Integrated Circuit (ASIC) for Silicon Photo-Multipliers (SiPM) detectors, used in the axial architecture based Time of Flight (ToF) Brain-PET scanners, readout. The current pulses obtained at the output of SiPM arrays are transformed into voltages with the help of charge resistances and then passed to the low noise and high bandwidth preamplifier stages. The amplified pulses are simultaneously passed to the pulse detection modules and the low-pass Sallen-Key filtering stages. The cut-off frequency of the filtering stages is selected as 80 MHz. The denoised pulses are conveyed to the discrete times delay lines (DLs). DLs operate at a 200 MHz sampling frequency and are founded on the base of a novel parallel architecture in place of the classical bucket bridge realization. Each detection module sums up the conditioned pulses of the SiPM pair, mutually aligned 180 degrees apart, and compares its mangnitude with a Leading Edge Discriminator (LED). LEDs outputs are employed by the coincidence detection and address encoding module. DLs are parameterized in order to achieve an effective baseline of around 140 ns while properly coping with the processing delays of the pulse detection, the coincidence detection and the address encoding modules. In the case of a coincidence detection, the concerned delayed pulses are selected by piloting two multiplexers with encoded address and are passed to the post processing modules. The selection process avoids the number of false events processing. It improves the sensitivity, processing efficiency and power consumption of the system. The ASIC is implemented on the 0.35 μm BiCMOS technology. The proposed ASIC functionality is verified with post layout simulations. The typical power consumption is respectively 60.4 mW and 4.693 W for a single channel and for the whole ASIC. Results have confirmed the effectiveness of suggested solution for the SiPM detectors signals readout and selection for Brain-PET applications.

1.3 V supply voltage, high bandwidth, 100 nA minimum amplitude BiCMOS voltage-controlled current source

A voltage-controlled current source in 0.35 μm BiCMOS technology is presented. A linear relationship between the control voltage and the output current is achieved by using first generation current conveyors in configuration of simple voltage-to-current converters. The control voltages of the DC and the AC output currents are completely independent of each other. The current source is intended for the generation of small currents in a sub-microampere range and in a frequency range of a few hundreds of megahertz. The measured and simulated results confirm that the smallest amplitudes of the generated currents are down to 100 nA, with a single supply voltage of 1.3 V. The small-signal bandwidth ranges from 15 up to 900 MHz.

Impact of TSV location in HVIC on CMOS operation: A mixed-mode TCAD simulation study

In this paper, a stacked 3D-technology is proposed to integrate the high voltage (HV) cLDMOS with the low voltage (LV) CMOS using TSV. The impact of the (0.0/42.0 V) HV signal of the future automotive applications on the performance of the LV CMOS inverter, implemented on the standard 0.35 μm BiCMOS technology, is investigated. This impact is performed utilizing a mixed mode simulation by using an equivalent SPICE models for the CMOS devices and finite element method (FEM) for the bulk regions. The CMOS output current is taken as an indicator for the substrate perturbations due to the switching of the applied signals. It is demonstrated that the influence of the HV on the performance of the CMOS signal is dependent on the location of the TSV. This effect can be minimized by adding a P+ guard-ring between the pMOS device and the TSV using the same mask of the nMOS P-WELL active area.

A 12–27 GHz SiGe BiCMOS VGA with phase shift variation compensation

This paper describes a 12–27 GHz VGA with low phase shift variation and dB-linear gain. A pre-distortion technique for extending the gain tuning range is employed to allow a dB-linear dynamic range of 31 dB, and a compensation structure for reducing the phase shift variation is adopted to make the phase shift varies less than 4° within the entire gain range. Besides, a DAC cell is innovatively introduced to achieve the dB linearity and low phase shift variation balance. A fourth-order LC-ladder filter is used for input matching and a peak inductor technique is used to broaden bandwidth of the VGA. The proposed variable gain amplifier operating in Ku and K bands is implemented in 0.18 μm BiCMOS technology. The simulation results show that the input and output return loss are less than −10 dB in the whole work frequency band, an IIP3 of −2.8 dBm, an IP1dB of −12 dBm and a power consumption of 62.1 mW are achieved at maximum gain mode in center frequency.

Analysis and Design of a Linear Digital Programmable Gain Amplifier in a 0.13 µm SiGe BiCMOS technology

AbstractThis paper presents the analysis and the design of a fully-differential digital programmable gain amplifier (PGA) in a 0.13 µm BiCMOS technology. The PGA has a gain control range of 31 dB with 1 dB gain step size and consumes 284 mW from a 3.6 V power supply. At a maximum gain of 25 dB, the PGA exhibits a 3-dB bandwidth of 10.1 GHz. The measured gain error for all 32 possible gain settings is between –0.19/+0.46 dB at 1 GHz. Up to 13 GHz the third harmonic distortion

A 2–22 GHz low-imbalanced active balun in 0.18 μm SiGe BiCMOS technology

A 2–22GHz broadband active balun using 0.18μm BiCMOS technology is presented. In this paper, an analysis of the imbalance of the active balun and the optimization method are given. The proposed active balun achieves a low-imbalanced performance. The imbalance of the differential output is less than 0.26dB in amplitude and less than 0.80° in phase. Using active inductor technique, the active balun results in a compact area of 0.74×0.67mm2, including bandgap circuit and all pads. The core active balun has a power consumption of 42mW from 3.3V supply voltage.

A low-voltage low-power 0.25 µm integrated single transistor active inductor-based filter

In this paper we present a 0.25 µm BiCMOS Technology bandpass filter implementation based on a single transistor Active Inductor (AI). The high-Q AI integrated circuit is designed by the use of a single transistor with a compensation network that allows to control both the inductance and its series resistance value. The AI-based high frequency bandpass filter has a center frequency of 2000 MHz (useful for radio and radar applications) and a 3 dB bandwidth of about 6 MHz with a quality factor of about 330. Moreover, a discrete prototype of the same AI has been also designed and measured. Measurements results on the discrete board have shown a 3 dB bandwidth of about 10 MHz, a noise figure of 6 dB, a ?10 dBm P1 dB compression point with 80 dB dynamic range. The power supply is 1.2 V with a power consumption of 800 µW showing low-voltage low-power operation capability together with good general performances.

200 μm APD OEIC in 0.35 μm BiCMOS

An optoelectronic integrated circuit (OEIC) in a 0.35 μm BiCMOS technology is presented. The receiver designed for optical wireless communication and communication over plastic optical fibre for data rates up to 2 Gbit/s has a 200 μm diameter avalanche photodiode (APD). Thanks to a thick intrinsic zone the APD has a low capacitance of 0.5 pF. The chip requires a supply voltage of 3.3 V and has a current consumption of 76 mA. The OEIC provides a single-ended output swing of 550 mV on 50 Ω and a total transimpedence of 260 kΩ with a bandwidth of 1.08 GHz. The OEIC achieves a sensitivity of −32.2 dBm at a BER of 10−9 for a data rate of 2 Gbit/s.

High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators

A hybrid arrangement for an optical transmitter sub-system comprising a linear driver fabricated in IHP SiGe 0.13 µm BiCMOS technology with an InP segmented Mach-Zehnder modulator is described. The proposed scheme, with direct interface to the digital to analog converter, is suitable for coherent high order modulation formats intended for data transmission over optical fiber at a wavelength of 1550 nm. In this paper, a partial prototype, consisting of a single driver core and modulator segment is demonstrated. The driver core features an output differential voltage of 2.5 Vpp, a gain of 9 dB and a 3 dB bandwidth of 32 GHz. Linearity is evaluated through total harmonic distortion measurements. With on---off-keying modulation, electro-optical eye diagram measurements of the single segment demonstrate successful operation up to 40 Gb/s data rate. While exhibiting clear capability for high speed operation, these results serve also to explore the boundaries of the proposed hybrid configuration.

Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology

This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

Performance of standard and double‐sided 3D‐radiation detectors under the impact of a temperature pulse

In this Letter, a comparison of the electrical performances of a standard and a double-sided 3D-radiation detectors using TCAD simulations is performed. The transient simulation is used to investigate the charge collection performance by swamping the detector with a uniform concentration of EHPs (75 e-h pairs/µm), chosen to give the same total number of carriers as a minimum ionising particle. Both detectors can be biased with the same voltage level of the readout circuitry in the standard 0.35 µm BiCMOS technology, but the standard full 3D structure is preferred for its high collection charge which means high signal to noise ratio. Finally, the impact of a temperature (300−400 K) pulse with fast transition times is studied. The impact has no significant effect on the collection current waveform of the standard but it has a big influence of the current waveform of the double-sided 3D-detectors. This makes the standard 3D-detector favourable than the double-sided 3D-detector in a harsh environment.