Impact of TSV location in HVIC on CMOS operation: A mixed-mode TCAD simulation study

Abstract

In this paper, a stacked 3D-technology is proposed to integrate the high voltage (HV) cLDMOS with the low voltage (LV) CMOS using TSV. The impact of the (0.0/42.0 V) HV signal of the future automotive applications on the performance of the LV CMOS inverter, implemented on the standard 0.35 μm BiCMOS technology, is investigated. This impact is performed utilizing a mixed mode simulation by using an equivalent SPICE models for the CMOS devices and finite element method (FEM) for the bulk regions. The CMOS output current is taken as an indicator for the substrate perturbations due to the switching of the applied signals. It is demonstrated that the influence of the HV on the performance of the CMOS signal is dependent on the location of the TSV. This effect can be minimized by adding a P+ guard-ring between the pMOS device and the TSV using the same mask of the nMOS P-WELL active area.