Mixer Topology Research Articles

Power-area evaluation of various double-gate RF mixer topologies

We analyze the suitability of the double gate MOSFETs (DG MOSFETs) for RF-mixer applications from the point of optimizing the transconductance gain, power consumption, and area. Mixer topologies using the 0.13-μm conventional MOSFETs, simultaneously driven DG MOSFETs (SDDG) and the independently driven DG MOSFETs (IDDG) are compared using extensive device simulations. In the frequency range 1-40 GHz, our simulation results show that the mixer circuits realized using the SDDG technologies show an order of magnitude lower power-area product, for a given transconductance gain, compared to the conventional and the IDDG technologies.

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.

A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.

A Low-Noise, High-Gain Single-Ended Input Double-Balanced Mixer

A noble single-ended input, double-balanced mixer topology is proposed. The mixer adopts a transconductance stage that amplifies the input and then converts it into differential currents leading to overall performance advantage compared to prior CG(common-gate)-CS(common-source)-based transconductance-stage mixer topologies without requiring additional power dissipation or extra transistor. The key specifications are compared with those of reported similar topologies, based on simulations.

Balanced subharmonic mixers for retrodirective-array applications

The drawback of conventional Pon retrodirective antenna systems is the requirement of a local oscillator (LO) working at approximately twice the receive frequency. This limits the use of these systems to rather moderate frequencies where such an oscillator can be obtained. To overcome this problem, a new phase conjugate mixer topology is proposed, whereby the use of a harmonic mixer instead of the conventional fundamental type effectively halves the LO frequency requirement. Another significant problem of conventional Pon phase conjugate mixers is the small spacing in frequency, typically only a few 0.1% of the carrier frequency, between RF, IF, and LO frequency. In this paper, we have overcome this problem by introducing a double balanced structure with a novel phasing strategy. The phasing circuit automatically cancels the RF and LO signal at the system's output port, giving 36-dB RF/IF, and 34-dB LO/IF isolation for a 970-MHz IF and 990-MHz RF signal. The new mixer structure proposed here is an attractive proposition for use in retrodirective antenna arrays significantly enhancing their potential for application in the millimeter-wave frequency range.

Current-reuse bleeding mixer

A novel mixer topology is proposed. The proposed mixer bleeds the driver stage current using a current source, the current source being used as part of the driver stage. Comparison with conventional mixers shows that the topology leads to better performance in terms of conversion gain, linearity, noise figure, and LO isolation.

Design Theory and Performance of 1-GHz CMOS Downconversion and Upconversion Mixers

A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 μm CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 μm CMOS technology, has been designed to achieve a NF of around 12 dB.

Monolithic RF active mixer design

An overview of monolithic radio-frequency (RF) active mixer design is presented. The paper is divided into two parts. The first part discusses the performance parameters that are relevant to the design of downconversion mixers, and how they affect the system performance. The second part presents three common kinds of mixer topologies, namely, unbalanced, single-balanced, and double-balanced designs. This paper concentrates on active mixers only, The advantages and disadvantages, as well as the design and optimization techniques for the three kinds of mixers, are discussed.

Low-noise Ku-band MMIC balanced P-HEMT upconverter

An enhanced design methodology for a low-noise Ku-band monolithic balanced high electron mobility transistor (HEMT) upconverter and its performance are presented in this paper. The mixer topology consists of a common source/common gate HEMT pair that performs the mixing and balun functions. A detailed study has been done to establish the role of the transistor model elements in the performance of the mixer. Based on this study, a new analysis is proposed to optimize the operating point of the mixer in order to get a tradeoff between conversion gain and port isolations. To combine the LO and intermediate-frequency (IF) signals, active circuits were used, as well as a high-pass filter in order to improve the isolations. The circuit size, including the filter and the combiners, is 3 mm/sup 2/. On-wafer measurements show a conversion gain over 2.5 dB, with only 3 dBm of LO power. A LO/RF isolation over 27 dB was measured in the whole LO band. The LO/IF isolation is over 27 dB thanks to the low reverse gain of the combiner HEMT's. A single sideband noise figure of 7.3 dB has been obtained.

A CMOS dual-channel, 100-MHz to 1.1-GHz transmitter for cable applications

A dual-channel wide-band transmitter for cable applications is presented that has more than a decade frequency coverage. The chip consists of two parallel transmitters that are both fully operational from 100 MHz up to 1.1 GHz. Using a single-ended current-mode output topology, the radio-frequency (RF) output signals are lossless combined by summing the output currents. The third-order harmonic of the oscillator signal is filtered by a wide-band polyphase filter. The complex filtering operation is mathematically described in this paper. The on-chip integrated oscillators have a measured 55-1200 MHz tuning range. Using the polyphase filter, a linear mixer topology, and a linear output driver, all distortion components are below -40 dBc. All intermodulation products of the two channels are smaller than -48 dBc. In this way, it is guaranteed that the parallel channels do not disturb the other channels in the frequency band even without any channel-specific filtering. Each channel delivers the designed -16-dBm RF output signal. The measured transmitter noise floor is situated at -139.8 dBc/Hz. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

An actively balanced GaAs HBT-Schottky mixer for 3-V wireless applications

Here we present a novel low-voltage active mixer topology which enables 3-V double-balanced active mixer operation from wide-bandgap GaAs-based heterojunction bipolar transistors (HBTs). The compact mixer design integrates directly coupled active radio frequency (RF) and local oscillator (LO) transformer baluns with a Schottky-diode ring-quad to form a double-balanced mixer which operates from DC to 5 GHz. Biased with a low 3-V supply and operated as a down-converter with a fixed LO at 800 MHz and 0 dBm, the mixer achieves 9.4-dB conversion gain (CG) at 1 GHz with positive CG out to 4 GHz and an IP3 of -5 dBm. The LO-IF isolation is >20 dB while the 2-2 spur suppression is >20 dB over a broad 1-5 GHz RF input band. The novel 2.1/spl middot/V/sub BE/ supply design topology allows 3-V operation from the high turn-on voltage GaAs HBT's, making them suitable for portable wireless applications, and can enable 1.5-V operation for Si, Si-Ge, and InP BJT/HBT technologies.

A 1-GHz CMOS up-conversion mixer

A high-frequency linear MOS mixer topology is presented for the implementation of a 1-GHz up-conversion mixer in a standard 0.7-/spl mu/m CMOS technology. The high output bandwidth has been achieved by the development of an nMOS-only current amplifier that converts the modulated current of the nMOS mixing transistor biased in the linear region to the RF output voltage.

A 1.5 GHz highly linear CMOS downconversion mixer

A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 /spl mu/m CMOS process. It takes up 1 mm/sup 2/ of total chip area and its power consumption is 1.3 mW from a single 5 V power supply. >

A 6 GHz 68 mW BiCMOS phase-locked loop

The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 /spl mu/m, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset. >

Double balanced mixers using active and passive techniques

A variety of microwave double-balanced mixers, using dual-gate FETs or diodes as the mixing nonlinearities, have been fabricated in planar monolithic circuit technology. The mixer topologies, which use active balancing methods, eliminate the need for large suspended substrate structures, thus minimizing circuit area and facilitating integration. These approaches also eliminate IF extraction problems and allow the best performance characteristics of FETs and diodes to be combined. The mixers are insensitive to DC bias and RF termination variations and require only one balun, which can be active or passive. They exhibit excellent decade-band performance with overlapping frequency response on all ports.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>