Mixer-first Receiver Research Articles

A 22-mW 0.9-2-GHz mixer-first receiver 8-phase overlap-suppressed 1/4 duty cycle LO for harmonic rejection

This paper presents a mixer-first wideband receiver front-end designed to achieve high linearity and harmonic rejection while minimizing power consumption. The proposed RF front-end adopts LO overlap suppression technology and uses 25 % duty cycle LO for 8-phase operation. In addition, the passive mixer with implicit capacitive stacking provides passive gain to the useful signal and improves harmonic rejection. The total power consumption of this work is less than 22 mW, the majority of which is consumed by the baseband amplifier and buffer, making it superior to existing active harmonic suppression RF front-ends in terms of low power consumption. The receiver is designed in TSMC 65-nm technology with an active area of 0.44 mm2 and is suitable for various communication standards from 0.9 GHz to 2 GHz. Post-layout simulation results show that < −15 dB S11, 16.7-dBm OOB-IIP3@80 MHz, 3.7–6.7 dB DSB-NF, 46.4–49.5 dB total system voltage gain and HRR3 of 35.4–42 dB are achieved. No active components are required for harmonic recombination.

A 60–90 GHz Mixer-First Receiver With Adaptive Temperature-Compensation Technique

A 60–90 GHz Mixer-First Receiver With Adaptive Temperature-Compensation Technique

Lung Mechanics Tracking With Forced Oscillation Technique (FOT) Based on CMOS Synchronous Demodulation Principle.

In this paper, an area-efficient CMOS integrated solution for lung impedance extraction is presented. The lock-in principle is leveraged for its high effective bandpass selectivity, to acquire information about the airways, through stimulation by FOT (Forced Oscillation Technique). The modulated pressure and flow signals are down-converted by a quadrature voltage commutating passive mixer-first receiver. In addition to its linearity, and unlike the Gilbert cell, it can be biased at zero dc current to alleviate flicker noise contributions. The proposed solution is designed and fabricated in 0.18µm TSMC technology. The chip occupies an active silicon area of 4.7 mm2 (including buffers and pads) and dissipates 429.63 µW. The proposed approach offers real time tracking of respiratory mechanics and is expected to be a promising solution for portable health monitoring and cost-effective biomedical devices.

A Millimeter-Wave Mixer-First Receiver With LO Waveform Shaping Using Varactors

A mixer-first receiver is proposed, which uses an overlap-suppressed local oscillator (LO) signal for the mixer switching. A sinusoidal LO wave can be shaped into a sharper waveform by adding a second-harmonic component to the fundamental one. This is readily achieved by integrating accumulation MOS varactors with LO buffers. The receiver is implemented in a 28-nm bulk CMOS and achieves an input 1-dB gain compression power in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 12.6 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 14.3 dBm and a noise figure (NF) in the range of 8.4–9.6 dB at frequencies of 24–29 GHz while consuming 12.6-mW power.

A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer

This article presents a low-power passive mixer-first receiver (MFRX) with an N-path harmonic-rejection (HR) transformer-mixer for narrowband Internet-of-Everything (IoE) applications. Composed of only switches and capacitors, the N-path HR transformer-mixer integrates the behavior of a transformer and harmonic recombination into the passive mixer itself, providing voltage gain, HR, and high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> filtering before any active components. A prototype RX in 22-nm fully-depleted silicon-on-insulator (FD-SOI) occupies 0.064 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\mathbf{2}$</tex-math> </inline-formula> and operates from 300 MHz to 3.0 GHz while consuming 0.6–1.8 mW. It achieves 3.4–4.8-dB noise figure (NF), 14–18-dBm out-of-band (OB)-input-referred third-order intercept point (IIP3), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-5$</tex-math> </inline-formula> –0-dBm OB-B1dB, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-8$</tex-math> </inline-formula> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-3$</tex-math> </inline-formula> -dBm H3/H5-B1dB, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 1-dB NF degradation with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-15$</tex-math> </inline-formula> -dBm OB blocker.

A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA

In this letter, we proposed a highly linear mixer-first receiver with a discrete-step attenuator (DSA) and a noise-shaping TIA. A resistor-reuse technique is devoted to improving linearity and attenuation flatness of the DSA with frequency independance, and a negative impedance chopping method is proposed to reduce the in-band noise of the TIA. Measurement results show that the receiver achieves > 13 dBm IIP3 and in-band noise floor has been depressed by 4 dB, with only consuming 2.82 mW under 1.3 V supply.

Second-Order Transimpedance Amplifiers in Mixer-First Receivers: Design for Optimum Blocker Tolerance

A design-oriented analysis of a transimpedance amplifier (TIA) reveals the optimum compression-free dynamic range for downconverted blockers lying in its 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order transition band. The unique circuit topology is chosen to eliminate low-frequency zeros of the transfer function to TIA output with only one OpAmp. Two approaches lead to TIA designs with or without capacitive positive feedback. Both configurations are analyzed and discussed. Simple and accurate design equations allow the component value to be selected straightforwardly. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\omega_0$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> of the two poles are independently controlled. Analytical expressions for out-of-band (OOB) linearity are derived, explaining different distortion mechanisms from both gate and drain voltages of a FET. The FET gate voltage is shown to affect the distortion even if its swing is much lower than the drain voltage swing. The design fully benefits from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order filtering, yielding optimum blocker tolerance. Power dissipation is limited by the requirements for noise figure and independent pole control. A mixer-first receiver that operates from 1 to 7 GHz is realized on 65 nm RF-SOI CMOS. It displays <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 31.1 dBm OOB input-referred third-order intercept point (OOB-IIP3), and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 11.8 dBm OOB blocker 1-dB compression point (B1dB). The TIA consumes 22 mW. The prototype verifies the TIA design.

A Wireless Soil pH and Conductance Monitoring Chip Powered by Soil Microbial and Photovoltaic Energy Cells.

This paper presents an energy-autonomous wireless soil pH and electrical conductance measurement IC powered by soil microbial and photovoltaic energy. The chip integrates highly efficient dual-input, dual-output power management units, sensor readout circuits, a wireless receiver, and a transmitter. The design scavenges ambient energy with a maximal power point tracking mechanism while achieving a peak efficiency of 81.3% and the efficiency is more than 50% over the 0.05-14 mW load range. The sensor readout IC achieves a sensitivity of -8.8 kHz/pH and 6 kHz·m/S, a noise floor of 0.92 x 10-3 pH value, and 1.4 mS/m conductance. To avoid interference, a 433 MHz transceiver incorporates chirp modulation and on-off keying (OOK) modulation for data uplink and downlink communication. The receiver sensitivity is -80 dBm, and the output transmission power is -4 dBm. The uplink data rate is 100 kb/s using burst chirp modulation and gated Class E PA, while the downlink data rate is 10 kb/s with a self-frequency tracking mixer-first receiver.

A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain

In this paper, a mixer-first receiver frontend with dual-feedback baseband is proposed. The negative resistive and positive capacitive feedback paths are both applied to single-stage inverter-based operational transconductance amplifier (OTA) with fewer poles, to cover a wide BB frequency range. The [Formula: see text]-path filtering at the RF side and second-order filtering at the BB side inhibit out-of-band blocker interferences. The receiver frontend is designed in 65 nm CMOS. Simulation results display an NF of 2.1 dB across 306 MHz IF bandwidth, and a maximum gain of 33 dB from 1 to 3 GHz LO frequency range. The in-band and out-of-band IIP3 are -13 and 16 dBm, respectively. The receiver core draws 40 mW at 1 GHz LO frequency.

A Low-Noise W-Band Receiver in a 28-nm CMOS Technology

A passive mixer-first receiver architecture operating at a frequency range between 70 and 86 GHz, together with a two-stage LO buffer and a low noise IF amplifier, is presented and designed in a 28-nm bulk CMOS technology. The receiver achieves a single-sideband noise figure (SSB NF) of less than 10 dB for IF frequencies above 400 kHz with a minimum of 9 dB above 1 MHz. The implemented chip features a voltage gain of about 14 dB and a 1-dB compression point of −5 dBm. The receiver core occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {0.09}~{\text {mm}^{2}}$ </tex-math></inline-formula> and consumes 55 mA from a 1.8-V power supply including all ON-chip biasing circuits.

A Mixer-First Receiver With Class-F Adiabatic Switching

This letter introduces the use of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">class-</i> F adiabatic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">switching</i> in a mixer-first 2.45-GHz ISM-band receiver. By using the principle of adiabatic switching with a class-F VCO, a resonant multiharmonic drive for an N-path-based mixer-first receiver is generated, resulting in a reduced power consumption while maintaining a good mixer noise figure (NF). To optimize the area, coupled inductors in the VCO are used. By employing a switched capacitor (SC) feedback network in the baseband (BB) amplifier, a proper input matching and flexible common-mode (CM) bias is achieved. A packaged chip implemented in 28-nm CMOS achieves a low-power consumption of 3.5 mW with a gain of 22 dB and an NF of 7.4 dB.

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internet-of-Things (IoT) applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-of-band linearity simultaneously while using at least 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal–oxide–semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype—including a 2:6 transformer—occupies only 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area. Operating in the frequency range of 1.8–2.8 GHz, the front end provides a 45–47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7–2.5 mW of power to achieve < 6-dB NF, ~24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.

Design of High-Linearity Mixer-First Receivers for mm-Wave Digital MIMO Arrays

A 10–35-GHz mixer-first receiver is proposed for use in digital multiple-input–multiple-output (MIMO) arrays. Techniques are proposed to enhance the linearity of such receivers, both at baseband and the RF mixer switches. Techniques to mitigate charge sharing due to local oscillator (LO) overlap are also proposed. Detailed simulation results are provided to illustrate the benefits of these techniques. An integrated circuit prototype is fabricated in 28-nm bulk CMOS and fully characterized. The receiver has built-in programmability to tradeoff gain for linearity. The receiver achieves a peak in-band IIP3 of +14.1 dBm, a peak gain of 14.5 dB, and a noise figure of 12.5 dB, in its nominal setting.

A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain

This article presents a 2.4-GHz 65-nm CMOS fully integrated nonlinear mixer-first receiver (RX) for the Internet of Things (IoT). To power efficiently improve the in-band interference resilience, we propose an inverter-based envelope-biased low noise amplifier (IBEB-LNA), which exploits dynamic biasing voltage generated from its input signal envelope to suppress the interferer in the amplitude domain. The achievable carrier-to-interference ratio (CIR) at ±3 and ±5 MHz is −45/−59 and −66/−65 dB, respectively. The proposed RX is suitable for ON–OFF keying (OOK) modulation with a 307-kb/s data rate, and the corresponding sensitivity is −83 dBm for keeping 0.1% bit error ratio (BER). The total power consumption is 2.05 mW.

A Wideband 62-mW 60-GHz FMCW Radar in 28-nm CMOS

This article presents an ultralow-power 60-GHz indoor frequency-modulated continuous-wave (FMCW) radar in 28-nm CMOS. The radar front end employs a tunable matching network (TMN), which tracks the chirp frequency and supports a 17% fractional bandwidth, covering unlicensed 60-GHz bands (57-66 GHz). A frequency sixtupler chain (x6) in the transmitter (TX) provides an output power of 8.1 dBm while achieving >20% dc-to-RF efficiency. A mixer-first receiver (RX) front end followed by a source degenerated high-pass (HP) filter suppresses TX-to-RX leakage (spillover) and induces minimal spillover-to-target intermodulation. The RX exhibits a 10.5-dB noise figure (NF) at 60 GHz with only 5.6-mW power consumption, making it suitable for an MIMO array. The radar IC with its DSP platform fully demonstrates its capability in indoor sensing scenarios. The duty-cycling compatible design enabled by the 1- μs radar startup time consumes 62 mW/18 mW in continuous mode/6.25% duty-cycled mode, a record low dc power compared to the state-of-the-art radars in this frequency range.

Impedance Transparency and Performance Metrics of HBT-Based N-Path Mixers for mmWave Applications

MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> HBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core.

Mm-Wave Mixer-First Receiver With Selective Passive Wideband Low-Pass Filtering

The front-end of a conventional millimeter-wave receiver (RX) consists of a bandpass filter (BPF) and low-noise amplifier (LNA) prior to the frequency down-conversion mixer. In interference-limited wireless channels, it is more footprint and power efficient to remove the BPF and LNA, and realize the mixer as a “passive” switching scheme. The noise figure of this passive mixer-first RX is improved when numerous such RXs are placed in a phased array or multi-input multi-output (MIMO) configuration. The passive switching mixer can be followed with an on-chip selective passive low-pass filter (LPF) with a small footprint given the large channel bandwidth that is typical in mm-wave applications. In this article, system and circuit design aspects of mm-wave passive mixer-first RXs are discussed and validated by a proof-of-concept 65-nm CMOS prototype. The implemented RX operates in the 21-29-GHz frequency range with 0.5-GHz instantaneous single-sideband (SSB) bandwidth, and achieves stopband to passband rejection of >49 dB, an in-band ICP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1 dB</sub> of -6 dBm, and out-of-band B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1 dB</sub> > 3.4 dBm.

Parametric Downconverter for Mixer-First Receiver Front Ends

In this article, we present a parametric downconverter that may be used in a mixer-first receiver front end. In such a receiver, the first mixer should offer a satisfactory low-noise figure (NF), high conversion gain (CG) to suppress the noise contribution of the next stages, and high linearity to avoid receiver saturation in the presence of interferences. Parametric mixers are known to offer parametric CG for frequency upconversion with no fundamental noise penalty due to its parametric amplification nature. This work is the first experimental demonstration of a parametric downconverter that achieves positive gain and low NF. The proof-of-concept mixer with a center input frequency of 1.9 GHz and an output frequency of 1.45GHz is designed and implemented on PCB. The mixer achieves a measured peak CG of 10 dB and a 1-dB compression point of +7 dBm. Furthermore, the fabricated mixer achieves a minimum NF of 2.8 dB over its bandwidth.

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications

In this article, we propose a baseband noise-canceling receiver architecture to increase in-band linearity. A key feature of the architecture is that all active circuits are in baseband, including the low-noise transconductance amplifier (LNTA). The LNTA operating at baseband frequencies allows the use of feedback to increase the linearity. This article analyzes a tradeoff that exists between in-band linearity and noise in mixer-first receivers and shows how the proposed architecture breaks such tradeoff. The receiver targets high IF bandwidths, enabled by a transimpedance amplifier (TIA) composed of an OpAmp using only inverters. This article describes the stabilization mechanism of this OpAmp with a unity-gain bandwidth (UGB) of 7.6 GHz. The receiver is fabricated in 22-nm FDSOI CMOS. The measured results show an in-band IIP3 of > 9 dBm for an IF bandwidth of 175 MHz with sub-5-dB noise figure (NF) across 1-6-GHz local oscillator (LO) frequencies.

A Mixer-First Receiver With Enhanced Matching Bandwidth by Using Baseband Reactance-Canceling LNA

A mixer-first receiver (RX) with enhanced matching bandwidth (BW) is proposed. The enhanced matching BW is achieved by exploiting the input reactance (negative capacitance) exhibited in resistive feedback voltage-voltage low-noise amplifiers (LNAs), to create a second-order baseband impedance without any power or noise penalty. The technique is analyzed based on a linear time-invariant (LTI) model. An integrated 8-phase mixer-first RX prototype was fabricated in the TSMC 65-nm CMOS process as a proof of concept. The RX is capable of broadband operation and achieves wideband <; -10-dB matching of 40 MHz, with 36-dB RX gain, noise figure (NF) of 2.2-4.2 dB, B1dB of 14.5 dBm, out-of-band (OOB) IIP3 of 33 dBm, and 1-dB NF degradation for 5-dBm blocker power, at a frequency range of 0.5-2 GHz.