Mixed-signal Test Research Articles

Current conveyor based test structures for mixed-signal circuits

Current-mode designs for mixed-signal testing are presented. The proposed structures are based on the use of second generation current conveyors (CCII) and they can be applied for voltage or current testing of analogue or digital circuits. A simple current sensor for on-chip current monitoring is described, giving an accurate analogue output proportional to the variation of the quiescent current; experimental results show the functionality of the proposed configuration and its linear output characteristic. An analogue test structure for multiple test point observation is also presented. The operation of the proposed structure has been verified using the PSPICE simulator; experimental measurements have also been made using CMOS current conveyors.

The IEEE Boundary Scan Standard: A Test Paradigm to Ensure Hardware System Quality

Click to increase image sizeClick to decrease image sizeKey Words: Bountry scantestablitySystem testProduct quality Additional informationNotes on contributorsMeryem MarzoukiAbout the Authors: Meryem Marzouki received a Ph.D. in computer science from the National Polytechnical Institute of Grenoble in 1991. From 1987 to 1992, she was involved primarily in prototype validation of ICs in the framework of electron-beam testing. Since then, her main research interests have been artificial intelligence approaches for test and diagnosis. Her current work is related to the partial boundary scan board and MCM test and diagnosis, fuzzy logic-based diagnosis of analog devices, and high-level synthesis for testability at the circuit and system levels. Since 1992. she has been a researcher with the CNRS (French National Research Center) in charge of the Diagnosis of Complex System Group al TIMA Laboratory in Grenoble, France.Adam OsseiranAdam Osseiran received a Ph.D. in microelectronics in 1986 from the Polytechnic Institute of Grenoble. He has developed a self-testable microcontroller dedicated to transportation systems. He then joined the Polytechnic Institute of Lausanne (Switzerland) where he was responsible for the design and test center of integrated circuits. His main research interests are in the design and test of mixed-signal integrated circuits. He is one of the two European contact persons to the working group on the standardization of the mixed-signal test bus. He is currently professor of microelectronics at the Engineering School of Geneva.

Mixed signal test — techniques, applications and demands

The increasing importance of next generation test technology to provide high quality, low cost fault detection methodologies is becoming a big issue in the microelectronics industry. For digital ASICs, techniques such as I-ddq and built-in-self test are being introduced to supplement or in some cases replace stuck-at-testing that has been shown to be inadequate for the circuit complexities and quality levels demanded. For analogue and mixed signal ICs, a similar trend is evident. Increasing circuit complexity, higher performance and the demand for high quality levels is causing the industry to question currently used functional and specification based test programs. In addition, the escalating costs of production test equipment capable of measuring high performance device parameters is in many cases becoming a limiting factor. The authors review the current state-of-the-art in mixed signal and analogue test technology with particular reference to the consumer electronics industry. Trends in key issues such as design-for-test, fault simulation, defect detection, CAD and tester support are discussed and the possible future role of these techniques is proposed for the next generation of single chip analogue and mixed signal test systems.

P1149.4 Mixed-Signal Test Bus

The IEEE P1149.4 Mixed-Signal Test Bus Working Group has been busy developing a usable standard addressing analog testability issues for mixed-signal technologies. The Working Group's charter is to define, document, and promote the use of a standard mixed-signal test bus that can be used at the device and assembly levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in self-test structures in order to reduce test development time, testing costs, and improve test quality.This short article will update the reader with the current standard architecture proposal, explain how the architecture can be used in a test scenario, and challenge the reader to respond to the Working Group with solutions or observations concerning some current topics of debate within the group. This standard is still in the stages of finalization, and the ideas and constructs presented here are proposals generally accepted by the Working Group, but may still change for technical or other reasons.

Cost/benefit analysis of the P1149.4 mixed-signal test bus

After briefly describing the proposed IEEE P1149.4 mixed-signal test bus standard and its salient benefits, the author investigates detailed costs of implementing the standard on ICs. The benefits include continuous time access in voltage and current mode, measurement of parameters such as resistance, capacitance and delay, and true differential access. The cost increase can vary between 3 and 35%, depending on the initial die size and whether 1149.1 is already on the IC. Lastly, proposed alternatives and future acceptance are discussed.

Extending Design-for-Test Into the Analog and Mixed-Signal Domains

A growing need exists for the design and testing of mixed-signal communication systems. Among the many factors driving this need are the current high interest in personal communication devices, and a desire for ever faster information transmission rates over the existing telecommunication network. Many of today's communication systems are designed and tested using techniques that cannot be characterized as either digital or analog. The data being processed, and the processing techniques themselves, do not fall neatly into either the digital or analog categories. Two approaches to mixed-signal testing, using currently available test-set hardware and software, have been developed and are presented in this paper. The research being done on a third, experimental, self-test method — and the techniques for accessing internal test nodes — are also discussed.

Mixing signals and voltages on chip

The advent of silicon chips that operate at 3 V and combine both analog and digital circuitry is discussed, and the engineering issues associated with 3 V mixed signal design are examined. The use of mixed-signal circuitry in communications applications such as the Ethernet interface analog macrocell is considered. Mixed signal simulation and testing are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

LAN interface chip and mixed-signal testing developments

LAN interface chip and mixed-signal testing developments