Mixed-signal Interface Research Articles

A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

Memristors and memristor crossbar arrays have been widely studied for neuromorphic and other in-memory computing applications. To achieve optimal system performance, however, it is essential to integrate memristor crossbars with peripheral and control circuitry. Here, we report a fully functional, hybrid memristor chip in which a passive crossbar array is directly integrated with custom-designed circuits, including a full set of mixed-signal interface blocks and a digital processor for reprogrammable computing. The memristor crossbar array enables online learning and forward and backward vector-matrix operations, while the integrated interface and control circuitry allow mapping of different algorithms on chip. The system supports charge-domain operation to overcome the nonlinear I–V characteristics of memristor devices through pulse width modulation and custom analogue-to-digital converters. The integrated chip offers all the functions required for operational neuromorphic computing hardware. Accordingly, we demonstrate a perceptron network, sparse coding algorithm and principal component analysis with an integrated classification layer using the system. A programmable neuromorphic computing chip based on passive memristor crossbar arrays integrated with analogue and digital components and an on-chip processor enables the implementation of neuromorphic and machine learning algorithms.

A Fully Configurable Non-Linear Mixed-Signal Interface for Multi-Sensor Analytics

This paper presents a highly configurable non-linear compression scheme and its implementation as a configurable, compressive successive approximation register analog-to-digital converter (ADC). The non-linear ADC takes advantage of the input signal amplitude statistics and application sensitivity to maximize the information content of the digitized signal. This allows for potential power savings in the ADC conversion and the digital post-processing that follows it. This paper is the first mixed-signal interface that is fully configurable in terms of its non-linear quantization approach, supporting a wide variety of quantization functions. A 90-nm CMOS proof-of-concept chip operating at 33 kS/s is presented. The versatility and broad applicability of this proposal are further demonstrated with various case studies.

A 0.18-μm CMOS high-data-rate true random bit generator through ΔΣ modulation of chaotic jerk circuit signals.

A full-custom design of chaos-based True Random-Bit Generator (TRBG) implemented on a 0.18-μm CMOS technology is presented with unique composition of three major components, i.e., (i) chaotic jerk oscillator, (ii) ΔΣ modulator, and (iii) simple pre/post-processing. A chaotic jerk oscillator is a deterministic source of randomness that potentially offers robust and highly random chaotic signals and exhibits a distinctive property of smoothly balanced-to-unbalanced alternation of double-scroll attractors. The continuous-time 2nd-order ΔΣ modulator is introduced as a mixed-signal interface in order to increase a resolution of random bit sequences while no extra clock is required. The ΔΣ modulator is constructed mainly by a folded-cascode amplifier with sufficient gain and phase margin of 64 dB and 83°, respectively, and a high-speed comparator with a time constant of 2.7 ns. An uncomplicated structure of shift-registers is realized as a post-processing process. The bit sequence of the proposed TRBG successfully passes all statistical tests of NIST SP800-22 test suite, and the ultimate output bit rate is 50 Mbps. The physical layout of a chip area is 212.8 × 177.11 μm and the DC power dissipation is 1.32mW using a 1.8-V single supply voltage. This paper therefore offers a potential alternative to a fully embedded cryptographic module in ASIC applications.

High-Precision Mixed-Signal Sensor Interface for a Wide Temperature Range [0° – 300°C

Abstract Sensor interfacing is a crucial component for today's systems in many application domains. Especially in automotive and manufacturing fields, high temperatures are encountered. For extracting the typically small sensor signals, an interface near the sensor is needed to provide a high-accuracy and robustness. This results in challenges for circuit design and architecture to avoid temperature related non-ideal effects. In this contribution, we present a novel system architecture for a Wheatstone bridge interfacing system. By encoding the sensor signal in time domain and augmenting the system with additional obseravtions, we present a robust and precise sensor interface operating at up to 300°C. We present a realization of this concept proven to be accurate within ±1.3%FS over the full temperature range.

Asynchronous compressed beamformer for portable diagnostic ultrasound systems.

State-of-the-art portable ultrasound imaging systems employ a small transducer array and a low carrier frequency to fit stringent constraints on power and form factor, and this tends to compromise the ultrasound imaging quality. In this paper, we present a low-complexity low-power asynchronous compressed beamformer (ACB) for portable diagnostic ultrasound. The proposed ACB integrates asynchronous sampling and compressive sensing (CS), and is capable of reducing data conversion power and handling a large data volume at the mixed-signal interface. A high-rate continuoustime ternary encoding (CT-TE) scheme eliminates the need for interpolation filters and coordinate rotation digital computer (CORDIC) units typically used in a conventional architecture. A split-projection least squares (SPLS) signal reconstruction algorithm is applied that replaces high-cost nonlinear signal recovery with a series of low-complexity and independent linear problems. Experiments with measured ultrasound data demonstrate the proposed ACB architecture, and the SPLS reconstruction algorithm achieves 9-fold data compression compared with Nyquist sampling.

A wireless RF CMOS mixed-signal interface for soil moisture measurements

This paper describes a wireless RF CMOS interface for soil moisture measurements. The interface basically comprises a Delta-Sigma (ΔΣ) modulator for acquiring an external sensor signal, and a RF section where data is transmitted to a local processing unit. The ΔΣ modulator is a single-bit, second-order modulator and it is implemented using switched-capacitors techniques in a fully-differential topology. With a sampling frequency of 423.75 kHz and an oversampling ratio (OSR) of 256, the modulator achieves a dynamic range of 98.7 dB (16.1 bit). The output of the modulator is applied to a counter, as a first-order decimation filter, and the result is stored. Prior to transmission, data is encoded as a pulse width modulated signal and assembled in a frame containing preamble and checksum control fields. This frame is then transmitted through a power amplifier operating at 433.92 MHz in class-E mode. To evaluate the ΔΣ modulator performance, the bitstream was acquired and transferred to a personal computer to perform digital filtering and decimation using MATLAB. The soil moisture sensor is based on dual-probe heat-pulse (DPHP) method and is implemented by using an integrated temperature sensor and a heater. After applying a heat-pulse for a fixed period of time, the temperature rise, that is a function of soil moisture, generates a differential voltage that is amplified and applied to the mixed-signal interface input. The described interface can also be used with other kinds of environmental sensors in a wireless sensors network. The CMOS mixed-signal interface has been implemented in a single-chip using a standard CMOS 0.7 μm process (AMI C07M-A, n-well, 2 metals and 1 poly).

A TOTAL-DOSE HARDENING-BY-DESIGN APPROACH FOR HIGH-SPEED MIXED-SIGNAL CMOS INTEGRATED CIRCUITS

This paper describes design choices and tradeoffs made when designing total-dose hardness into an advanced CMOS integrated circuit. Closed geometry transistors are described and compared, emphasizing their radiation tolerant performance. Speed and area tradeoffs incurred in circuit design when using such closed geometry transistors are illustrated in the design of an advanced IEEE 1394 cable physical layer mixed-signal interface chip.

Digitally programmable dB-linear CMOS AGC for mixed-signal applications

Central to the design of a high-performance, high-dynamic mixed-signal interface circuitry is the design of a linear (in the db scale) automatic gain control (AGC) loop. Achieving this db-linear characteristic requires an exponential function and is therefore, not straightforward to implement with CMOS devices in strong inversion. The article in this column discusses a simple CMOS circuit design solution to this problem, The design is also digitally controlled, which should help in designing simple mixed-signal interfaces with low power consumption and less chip area.