Mixed-signal Hardware Research Articles

Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions

The increasing scale of neural networks and their growing application space have produced demand for more energy- and memory-efficient artificial-intelligence-specific hardware. Avenues to mitigate the main issue, the von Neumann bottleneck, include in-memory and near-memory architectures, as well as algorithmic approaches. Here we leverage the low-power and the inherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate neural network hardware inference based on passive arrays of MTJs. In general, transferring a trained network model to hardware for inference is confronted by degradation in performance due to device-to-device variations, write errors, parasitic resistance, and nonidealities in the substrate. To quantify the effect of these hardware realities, we benchmark 300 unique weight matrix solutions of a 2-layer perceptron to classify the Wine dataset for both classification accuracy and write fidelity. Despite device imperfections, we achieve software-equivalent accuracy of up to 95.3 % with proper tuning of network parameters in 15 x 15 MTJ arrays having a range of device sizes. The success of this tuning process shows that new metrics are needed to characterize the performance and quality of networks reproduced in mixed signal hardware.

Supervised training of spiking neural networks for robust deployment on mixed-signal neuromorphic processors

Mixed-signal analog/digital circuits emulate spiking neurons and synapses with extremely high energy efficiency, an approach known as “neuromorphic engineering”. However, analog circuits are sensitive to process-induced variation among transistors in a chip (“device mismatch”). For neuromorphic implementation of Spiking Neural Networks (SNNs), mismatch causes parameter variation between identically-configured neurons and synapses. Each chip exhibits a different distribution of neural parameters, causing deployed networks to respond differently between chips. Current solutions to mitigate mismatch based on per-chip calibration or on-chip learning entail increased design complexity, area and cost, making deployment of neuromorphic devices expensive and difficult. Here we present a supervised learning approach that produces SNNs with high robustness to mismatch and other common sources of noise. Our method trains SNNs to perform temporal classification tasks by mimicking a pre-trained dynamical system, using a local learning rule from non-linear control theory. We demonstrate our method on two tasks requiring temporal memory, and measure the robustness of our approach to several forms of noise and mismatch. We show that our approach is more robust than common alternatives for training SNNs. Our method provides robust deployment of pre-trained networks on mixed-signal neuromorphic hardware, without requiring per-device training or calibration.

Low Complexity Hybrid Precoding and Combining for Millimeter Wave Systems

In millimeter-wave (mmWave) systems, hybrid precoding/combining architectures are an attractive low-complexity alternative to the use of fully digital precoding. This is because of the reduction in the number of Radio-Frequency (RF) and mixed-signal hardware components. Hybrid precoding/combining design involves a combination of analog and digital processing that enables both beamforming and spatial multiplexing gains in mmWave systems. This paper presents an algorithm for hybrid precoding and combining designs in mmWave systems. The proposed design does not depend on the antenna array geometry, unlike the orthogonal matching pursuit (OMP) hybrid precoding/combining approach. Moreover, this algorithm allows hybrid precoders/combiners to perform close to the known optimal performance of unconstrained digital precoders and combiners. Simulation results verify that the proposed hybrid precoding/combining scheme outperforms the previous methods in the literature in terms of bit error rate (BER) and achievable spectral efficiency with lower complexity.

Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration

Recent integration of Resistive Random Access Memory (RRAM) with standard CMOS has spurred exploration of high-density and low-power in-memory computing. RRAM arrays are being intensely investigated for analog-domain Vector Matrix Multiplication (VMM) and Neuromorphic Computing. However, to exploit the advantages of RRAM over other forms of nonvolatile memories, mixed-signal circuit designers need to accommodate their device nonidealities, and design circuits to translate high-level deep neural network algorithms to mixed-signal hardware. This brief reviews the field of neuromorphic computing using hybrid CMOS-RRAM circuits, associated circuit design challenges, and potential approaches for their mitigation, followed by benchmarking of recent demonstrations.

Improving the efficiency of DNN hardware accelerator by replacing digital feature extractor with an imprecise neuromorphic hardware

Mixed-signal in-memory computation can drastically improve the efficiency of the hardware implementing machine learning (ML) algorithms by (i) removing the need to fetch neural network parameters from internal or external memory and (ii) performing a large number of multiply-accumulate operations in parallel. However, this boost in efficiency comes with some disadvantages. Among them, the inability to precisely program nonvolatile memory devices (NVM) with neural network parameters and sensitivity to noise prevent the mixed-signal hardware to perform a precise and deterministic computation. Unfortunately, these hardware-specific errors can get magnified while propagating along with the layers of the deep neural network. In this paper, we show that the inability to implement parameters of the already trained network with enough precision can completely stop the network from performing any meaningful operation. However, even at this level of degradation, the feature extractor section of the network still extracts enough information from which an acceptable level of performance can be achieved by just retraining the last classification layers of the network. Our results suggest that instead of just blindly trying to implement software algorithms in hardware as precisely as possible, it might be more efficient to implement neural networks with imperfect devices and circuits and let the network itself compensate for these imprecise computations by only retraining few layers.

Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error

This paper studies multi-stage capacitive mixed-signal matrix-vector multiplying digital-to-analog (MDAC) conversion topologies for highly energy-efficient, high-resolution, and high-dimensional MIMO analog processing systems. In order to mitigate nonlinearity due to radix errors and capacitive mismatch encountered in compact low-power MDAC realizations, we introduce stochastic successive approximation , or S2A, as an online optimization algorithm for adaptive array analog signal processing amenable to efficient implementation in massively parallel mixed-signal hardware. S2A offers a direct alternative to stochastic gradient descent overcoming several of its shortcomings, such as its sensitivity to model error, while improving on the rate and quality of convergence. S2A overcomes non-convergence typically encountered with gradient descent for non-convex optimization landscapes induced by a mismatch in capacitive multiplying digital-to-analog converter components when applied to adaptive analog signal processing. Experimental validation of S2A in mixed-signal hardware for real-time RF adaptive beamforming demonstrates 65 dB of over-the-air, multipath interferer suppression in fewer than 25 S2A iterations.

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

Mixed-signal integrated circuits (ICs) play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based first-order one-bit delta-sigma ( Δ Σ ) analog to digital converter (ADC) through proposing four attack and one defense models. The first attack manipulates the input signal to the Δ Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

A low power mixed signal correlator for power efficient sound signature detection and template matching

PurposeSensor networks have found wide applications in the monitoring of environmental events such as temperature, earthquakes, fire and pollution. A major challenge with sensor network hardware is their limited available energy resource, which makes the low power design of these sensors important. This paper aims to present a low power sensor which can detect sound waveform signatures.Design/methodology/approachA novel mixed signal hardware is presented to correlate the received sound signal with a specific sound signal template. The architecture uses pulse width modulation and a single bit digital delay line to propagate the input signal over time and analog current multiplier units to perform template matching with low power usage.FindingsThe proposed method is evaluated for a chainsaw signature detection application in forest environments, under different supply voltage values, input signal quantization levels and also different template sample points. It is observed that an appropriate combination of these parameters can optimize the power and accuracy of the presented method.Originality/valueThe proposed mixed signal architecture allows voltage and power reduction compared with conventional methods. A network of these sensors can be used to detect sound signatures in energy limited environments. Such applications can be found in the detection of chainsaw and gunshot sounds in forests to prevent illegal logging and hunting activities.

Hybrid MMSE Precoding and Combining Designs for mmWave Multiuser Systems

Hybrid analog/digital precoding architectures are a low-complexity alternative for fully digital precoding in millimeter-wave (mmWave) MIMO wireless systems. This is motivated by the reduction in the number of radio frequency and mixed signal hardware components. Hybrid precoding involves a combination of analog and digital processing that enables both beamforming and spatial multiplexing gains in mmWave systems. This paper develops hybrid analog/digital precoding and combining designs for mmWave multiuser systems, based on the mean-squared error (MSE) criteria. In the first design with the analog combiners being determined at the users, the proposed hybrid minimum MSE (MMSE) precoder is realized by minimizing the sum-MSE of the data streams intended for the users. In the second design, both the hybrid precoder and combiners are jointly designed in an iterative manner to minimize a weighted sum-MSE cost function. By leveraging the sparse structure of mmWave channels, the MMSE precoding/combining design problems are then formulated as sparse reconstruction problems. An orthogonal matching pursuit-based algorithm is then developed to determine the MMSE precoder and combiners. Simulation results show the performance advantages of the proposed precoding/combining designs in various system settings.

Limited Feedback Hybrid Precoding for Multi-User Millimeter Wave Systems

Antenna arrays will be an important ingredient in millimeter wave (mmWave) cellular systems. A natural application of antenna arrays is simultaneous transmission to multiple users. Unfortunately, the hardware constraints in mmWave systems make it difficult to apply conventional lower frequency multiuser MIMO precoding techniques at mmWave. This paper develops low complexity hybrid analog/digital precoding for downlink multiuser mmWave systems. Hybrid precoding involves a combination of analog and digital processing that is inspired by the power consumption of complete radio frequency and mixed signal hardware. The proposed algorithm configures hybrid precoders at the transmitter and analog combiners at multiple receivers with a small training and feedback overhead. The performance of the proposed algorithm is analyzed in the large dimensional regime and in single path channels. When the analog and digital precoding vectors are selected from quantized codebooks, the rate loss due to the joint quantization is characterized and insights are given into the performance of hybrid beamforming compared with analog-only beamforming solutions. Analytical and simulation results show that the proposed techniques offer higher sum rates compared with analog-only beamforming solutions, and approach the performance of the unconstrained digital beamforming with relatively small codebooks.

Building an on-chip spectrum sensor for cognitive radios

Next generation cognitive radio networks require an RF and mixed signal hardware architecture that can achieve low-energy, very wideband spectrum sensing. We survey state-of-the-art low-power CMOS building blocks as potential candidates for realizing such an architecture. For the critical analog-to-digital converter, we compare time-interleaved and frequency- interleaved architectures, including system- level simulations, and frequency-interleaving is shown to provide significant advantages. Measurement results from a 3.8 mW 5 GHz bandwidth analog domain frequency interleaver are presented to confirm the possibility of a very low-energy frequency domain digitizer. Coupled with DSP for calibration and signal feature extraction, this architecture has significant promise for cognitive spectrum sensing.

An Ultra-High Speed Emulator Dedicated to Power System Dynamics Computation Based on a Mixed-Signal Hardware Platform

This paper presents an ultra-high speed hardware platform dedicated to power system dynamic (small signal) and transient (large signal) stability. It is based on an intrinsic parallel architecture which contains hybrid mixed-signal (analog and digital) circuits. For a given model, this architecture overcomes the speed of the numerical simulators by means of the so-called emulation approach. Indeed, the emulation speed does not depend on the power system size. This approach is nevertheless not competing against high-performance numerical simulators in term of accuracy and model complexity. It targets to complement the numerical simulators with the advantage of speed, portability, low cost and autonomous functioning. The proof of concept is a flexible and modular 96-node hardware platform. It is based on a reconfigurable array of power system buses called Field Programmable Power Network System (FPPNS). Details on this hardware are given. Two benchmark topologies with, respectively, 17 nodes and 57 nodes are provided. Comparisons with a digital simulator are done in terms of speed and accuracy. The calibration of the system is explained and different applications are proposed and discussed. The promising results of this hardware platform show that the design of a fully integrated solution containing hundreds of power system buses can be achieved in order to provide a low cost solution.

VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling heterogeneous or multidiscipline systems. The paper has two objectives. The first one is modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e., discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are the Advance-MS from Mentor Graphics for VHDL-AMS and the AMS Simulator from Cadence Design Systems for Verilog-AMS. This paper shows that both languages offer effective means to describe and simulate multidiscipline systems, though using different descriptive approaches. It also highlights current tool limitations, since full language definitions are not yet supported.

Mixed-signal modeling with AleC++: Specific features of the HDL

Alecsis behavioral simulator and its mixed-signal hardware description language (HDL) AleC++ form an open simulation environment, where electronic circuits and non-electrical systems can be analyzed. This paper describes some of the features of AleC++ language, namely mainly those that are not in accordance with the IEEE standard for VHDL and VHDL-AMS, but are very useful for modeling complex systems.

An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing

Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power-in the order of trillions of operations per second (TeraOPS). Compared with conventional digital technology, cellular neural/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN chipset architecture has been developed-a mixed-signal hardware platform for CNN-based image processing. One of the nonstandard components of the chipset is the cache memory of the analog array processor, the analog random access memory (ARAM). This paper reports on an ARAM chip that has been designed and fabricated in a 0.5-/spl mu/m CMOS technology. This chip consists of a fully addressable array of 32/spl times/256 analog memory registers and has a packing density of 637 analog-memory-cells/mm/sup 2/. Random and nondestructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separate power supplies for the analog and the digital circuitry. This prototype features an equivalent resolution of up to 7 bits-measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing/reading to/from the memory registers are of 200 ns. I/O rates via the l6-line-wide I/O bus exceed 10 Msamples/s. Storage time at room temperature is in the 80 to 100 ms range, without accuracy loss.

A Programmable Imager for Very High Speed Cellular Signal Processing

In this paper a programmable imager with averaging will be described which is intended for averaging of different groups or sets of pixels formed by n × n kernels, n × m kernels or independent pixels of the array. This imager is a 64 × 64 array which uses passive pixels that can be randomly accessed. The read-outstage includes a sole charge amplifier with programmable gain, a sample-and-hold structure and an analog buffer. This read-out structure is different from other existing imagers with variable resolution since it uses a sole charge amplifier, whereas the normal structure is an operational amplifier per column plus a global operational amplifier. This structure will be described in detail indicating the advantages and disadvantages with respect to other imagers with averaging capabilities. This programmable resolution architecture can be more appropriate, and eventually, more efficient, when implementing very high speed Cellular Neural Network (CNN) processors in a CNN chipset—a mixed-signal hardware platform for CNN-based image processing. A significant processing time reduction can be obtained when decreasing the image resolution, and therefore the amount of information to be transferred to the CNN processor. This programmable resolution can also be used for fast image recognition and ulterior windowing at full resolution in a reduced area of the image, permitting a more accurate processing of the region of interest. In addition, full resolution images can still be obtained, as in commercial imagers which are usually included in CNN chipsets.

Behavioral Level Noise Modeling and Jitter Simulation ofPhase-Locked Loops with Faults Using VHDL-AMS

It is important to predict noise at the early stages of a top-down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator (VCO), power supply noise, and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally-verified theoretical predictions.