Mixed-signal Approach Research Articles

An 18–28 GHz dual-mode down-converter IC for 5G applications

Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {mm}^\ ext {2}$$\\end{document}. The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.

Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm2 and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts.

A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting

As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.

Special Issue “Smart IC Design and Sensing Technologies”

Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, from IoT applications to complicated medical devices. Moreover, circuit implementation, which could be based on a full analog or digital approach or, in most cases, on a mixed-signal approach, possesses a fundamental role in exploiting the full capabilities of sensing technologies. In addition, all circuit design methodologies include the optimization of several performance metrics, such as low power, low cost, small area, and high throughput, which impose critical challenges in the field of sensor design. This Special Issue aims to highlight advances in the development, modeling, simulation, and implementation of integrated circuits for sensing technologies, from the component level to complete sensing systems.

Sensitivity of a Chaotic Logic Gate

Chaotic logic gates or ‘chaogates’ are a promising mixed-signal approach to designing universal computers. However, chaotic systems are exponentially sensitive to small perturbations, and the effects of noise can cause chaotic computers to fail. Here, we examine the sensitivity of a simulated chaogate to noise and other parameter variations (such as differences in supply voltage). We find that the regions in parameter space corresponding to chaotic dynamics coincide with the regions of maximum error in the computation. Further, this error grows exponentially with a maximum likelihood rate constant of 3.5 iterations of the chaotic map. As such, we discuss the fundamental challenges of chaotic computing, and suggest potential improvements. Our Python simulation methods are open-source and available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/Noeloikeau/chaogate</uri> .

Memristor-Based Binarized Spiking Neural Networks: Challenges and applications

Memristive arrays are a natural fit to implement spiking neural network (SNN) acceleration. Representing information as digital spiking events can improve noise margins and tolerance to device variability compared to analog bitline current summation approaches to multiply–accumulate (MAC) operations. Restricting neuron activations to single-bit spikes also alleviates the significant analog-to-digital converter (ADC) overhead that mixed-signal approaches have struggled to overcome. Binarized, and more generally, limited-precision, NNs are considered to trade off computational overhead with model accuracy, but unlike conventional deep learning models, SNNs do not encode information in the precision-constrained amplitude of the spike. Rather, information may be encoded in the spike time as a temporal code, in the spike frequency as a rate code, and in any number of stand-alone and combined codes. Even if activations and weights are bounded in precision, time can be thought of as continuous and provides an alternative dimension to encode information in. This article explores the challenges that face the memristor-based acceleration of NNs and how binarized SNNs (BSNNs) may offer a good fit for these emerging hardware systems.

A Robust Mixed-Signal Cancellation Approach for Even-Order Intermodulation Distortions in LTE-A/5G-Transceivers

State-of-the-art radio frequency receivers for mobile communications inevitably show nonlinearities, mainly caused by constraints in the analog design of the low-noise amplifier and the mixer. In the widely-used direct-conversion architecture, especially even-order intermodulation products cause interference in the baseband, thereby severely deteriorating the receiver signal-to-noise ratio. While several proposed methods aim to cancel second-order distortions caused by transmitter self-interference, the mitigation of higher-order effects is rarely covered. In this brief, we present a novel scalable mixed-signal approach for cancellation of intermodulation distortions up to the sixth order. The interference signal is captured by means of an auxiliary receiver, which also allows to suppress interferences caused by external sources. The auxiliary receive signal serves as a basis for a real-time capable digital processing chain, which replicates and cancels the interference. The effectiveness of the proposed method has been verified using measurement data from real-world scenarios.

A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz—a 4 $\times $ improvement over state-of-the-art for comparable stability.

Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment

This paper addresses the development of a behavioral modeling abstraction methodology that reduces the model order complexity of the transistor level physical model describing the input–output (I/O) buffers that interface the digital (i.e., discrete) and the analog world in the high-speed digital communication I/O links. In fact, the proposed high-level hybrid automaton behavioral model (HABM) is analyzed as a mixed-signal modeling approach that combines both discrete and continuous abstractions. The modeling framework investigates the quantization of the on–off nonreturn-to-zero input signal to analyze the mixed signal behavior of the predriver and the analog dynamics of the I/O buffer’s last stage for easing the model’s extraction and running complexities while accurately predicting the I/O buffer’s nonlinear switching behavior under normal and overclocking conditions. The time decomposition of the input and state variables enables the approximation of the predriver’s nonlinear dynamic by means of digitally controlled linear dynamic filters. The filter’s outputs are multiplexed and integrated with the continuous-time nonlinear dynamic model of driver’s last stage output admittances. The implemented mixed-signal HABM presents more accurate transient simulation results than the I/O buffer information specification algorithm when assessing the signal integrity performance while alleviating the computational cost under overclocking operation.

A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.

Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level

Neuromorphic computing is non-von Neumann computer architecture for the post Moore’s law era of computing. Since a main focus of the post Moore’s law era is energy-efficient computing with fewer resources and less area, neuromorphic computing contributes effectively in this research. In this paper, we present a memristive neuromorphic system for improved power and area efficiency. Our particular mixed-signal approach implements neural networks with spiking events in a synchronous way. Moreover, the use of nano-scale memristive devices saves both area and power in the system. We also provide device-level considerations that make the system more energy-efficient. The proposed system additionally includes synchronous digital long term plasticity, an online learning methodology that helps the system train the neural networks during the operation phase and improves the efficiency in learning considering the power consumption and area overhead.

An FPGA-Based Phase Measurement System

Phase measurement is required in electronic applications where a synchronous relationship between the signals needs to be preserved. Traditional electronic systems used for time measurement are designed using a classical mixed-signal approach. With the advent of reconfigurable hardware such as field-programmable gate arrays (FPGAs), it is more advantageous for designers to opt for all-digital architecture. Most high-speed serial transceivers of the FPGA circuitry do not ensure the same chip latency after each power cycle, reset cycle, or firmware upgrade. These cause uncertainty of phase relationship between the recovered signals. To address the need to register minute phase shift changes inside an FPGA, we propose a design for phase measurement logic core having resolution and precision in the range of a few picoseconds. The working principle is based on subsample accumulation using systematic sampling over the phase detector signal. The phase measurement logic can operate over a wide range of digital clock frequencies, ranging from a few kilohertz to the maximum frequency that is supported within the FPGA fabric. A mathematical model is developed to illustrate the operating principle of the design. The VLSI architecture is designed for the logic core. We also discussed the procedure of the phase measurement system, the calibration sequence involved, followed by the performance of the design in terms of accuracy, precision, and resolution.

Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities. The driver has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality. A mixed signal approach that detects and compensates for NMOS and PMOS transistor resistance variation is presented. An analog circuit detects the driver's resistance variation, and a digital circuit controls an analog compensation circuit to maintain line impedance matching for all signal conditioning configurations of the driver. When maximum signal conditioning is enabled, the driver can transmit a 40Gbits/sec PRBS7 signal through a 10 in. FR4 channel. It achieves a differential eye-opening amplitude of 100mVppd and an eye-opening width of 0.8UI consuming 9.7mW of at-speed power. Simulations demonstrate that worst case impedance deviation from 50Ω due to process, voltage and temperature variation is 2.7%. The driver is designed in 28nm CMOS process using a 0.85V nominal supply voltage. It is simulated using HSPICE circuit simulator and mixed mode simulations tools.

A Soft-Defined Pulse Width Modulation Approach—Part II: System Modeling

In this work we model from a system design perspective the realization of a novel mixed-signal approach to pulse width modulation (PWM). The working principle for the approach, along with an implementation scheme comprised of a digital zero-positioning (ZP) followed by a proper digital-to-analog converter (DAC) and comparator, has been introduced in a companion paper. We here focus on analyzing the global system in order to get a model of its performances in terms of dynamic range and non-linearity. Since non-linearities and quantization noise occur between the ZP and the comparator, firstly, upstream models for them are provided; then their effect on the PWM signal is calculated by means of a downstream model of perturbations at the input of an ideal natural sampling PWM. Finally, an exhaustive formula for the resulting dynamic range is given and some configurations of practical interest are proposed.

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture

In this paper we propose a design of a dependable self-organizing and adaptive mixed-signal SoC. We introduce an Artificial Hormone System (AHS) as a general control mechanism, which addresses the goals of organic computing methodology. Regarding the coexistence of digital and analog components in SoCs, we developed two new AHS implementations, one pure analog approach and one mixed-signal approach. Besides the basics of the hormone based control mechanisms, especially for the analog domain, this paper adapts the AHS upon mixed-signal SoC and presents the evaluation of a completely simulated AHS-controlled SoC. This evaluation verifies the approaches including stability issues as well as upper timing bounds and shows the improvement achieved on the system reliability. We also state the advantages from the hormone system compared to other approaches, as well as the strong points of the different hormone systems to one another.

A circuit implementation of an ultra high speed, low power analog fully programmable MFG

In this article, an analog fully programmable membership function generator MFG is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled digitally or by mixed signal approaches, this structure is a fully programmable analog MFG. It is capable of modifying slope, position and height of output's current. The most distinguishing features of this MFG are its capability of generating ultra-high speed outputs reaching speeds as high as 200 MHz and consuming a very low amount of power. Due to the simple structure of this MFG, it consumes a small active area at the size of 20 μm × 30 μm. It is constructed of only 16 transistors. This MFG has been designed in 0.35 μm CMOS technology. The simulations have been done with Hspice using TSMC, BSIM3 V3.1 model.

The Universal Circuit Simulator: A Mixed-Signal Approach to $n$-Port Network and Impedance Synthesis

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided.

Design for Testability of CMOS Analog Sum-Product Error-Control Decoders

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation.

A Mixed-Signal Approach Towards Linear and Efficient $N$-Way Doherty Amplifiers

A mixed-signal approach for the design and testing of high-performance N-way Doherty amplifiers is introduced. In support of this, an analysis of N-way power-combining networks is presented-in particular, their optimum design-by examining the relationship between the drive conditions of the active devices and input power. This analysis makes no prior assumption on the network topology and facilitates free-to-choose levels for the high-efficiency power back-off points. By comparing the results of this analysis with prior work, it is shown that very specific drive conditions apply to traditional three-way Doherty amplifier implementations to obtain simultaneously high-efficiency and high-linearity operation. To support these conclusions, a 15-W three-way Doherty amplifier was constructed using Philips GEN4 LDMOS devices featuring three separate inputs to independently drive the main and peaking devices. By testing this three-way amplifier with a custom-built measurement setup, capable of providing multiple digitally controlled coherent RF input signals with high spectral purity, a unique flexible amplifier concept is created resulting in a record-high efficiency for LDMOS-based Doherty amplifiers over a 12-dB back-off power range

A MIXED-SIGNAL ROW/COLUMN ARCHITECTURE FOR VERY LARGE MONOLITHIC mm-WAVE PHASED ARRAYS

The range of mm-wave radio communications is severely constrained by high losses arising from the short wavelength and from atmospheric attenuation. Large phased arrays can overcome these limitations, but it is very difficult to realize them using present monolithic beamsteering IC architectures. We propose an alternative architecture for large monolithic phased arrays. The beam is steered in altitude and in azimuth by separately imposing vertical and horizontal phase gradients. This choice reduces IC complexity, making large arrays feasible. Since extensive digital processing provides robust amplitude control and reduces die area, the LOs are processed as digital signals. Being very sensitive to compression, the IF signals are processed as analog signals and distributed by means of synthetic transmission-line buses. With careful frequency planning, this mixed-signal approach can allow large phased arrays to operate at frequencies much higher than those achievable with pure analog design.