Mixed-signal Application-specific Integrated Circuit Research Articles

Nested Closed-Loop Control of Quasi-Static MEMS Scanners With Large Dynamic Range

This research discusses the challenges in implementing a fully electrical closed-loop control system for high-end applications of quasi-static microscanners, accounting at the same time for wide aperture, high-accuracy and wide-bandwidth. The discussion highlights how not only the ringing of the main mode, but also the presence of spurious modes and nonlinearity, impact the closed loop stability and accuracy. A novel control approach based on nested loops is conceived and implemented in the digital domain in a mixed-signal application-specific integrated circuit (ASIC). The developed versatile ASIC is designed to be coupled to different types of micromirrors, with fundamental frequency ranging from few hundred Hz to few kHz, by simply adjusting coefficients in the digital domain. The ASIC is here successfully operated with two micromirrors and results demonstrate saw-tooth position control at 28-32 deg field of view and up to 120 Hz refresh rate, while holding at the same time a tilt angle resolution of 25 mdeg r.m.s. (dynamic range of 60 dB) and a linearity error below 1%

Pulsed-Laser Testing to Quantitatively Evaluate Latchup Sensitivity in Mixed-Signal ASICs

Pulsed-laser testing is used to accurately determine single-event latchup (SEL) thresholds for static random-access memories (SRAMs) with different body-tie-to-drain spacings on a mixed-signal application-specific integrated circuit (ASIC), a study that could not be completed using only broad-beam heavy-ion testing. Two distinct approaches were employed with the first approach, an empirical correlation method, exploiting the complementary nature of broad-beam heavy-ion and laser testing. Various single- and dual-port SRAMs exhibited SEL thresholds ranging from 1 MeV-cm²/mg to over 100 MeV-cm²/mg, with a dual-port device possessing the smallest body-tie-to-drain spacing being latchup immune at the highest available test conditions (>300 MeV-cm²/mg). These results have been used to inform a follow-on ASIC design resulting in a significant improvement in chip-level SEL sensitivity. The second approach, a calculational method, uses pulsed-laser measurements and charge-deposition modeling to predict linear energy transfer (LET) thresholds without heavy-ion data. This calculational approach agrees with the empirical approach and therefore shows promise as a predictive tool for SEL threshold estimation, but further validation is required. Overall, these approaches can be effective tools for evaluating SEL susceptibilities and mitigation strategies.

A custom 70-channel mixed signal ASIC for the brain-PET detectors signal readout and selection

This paper presents a 70-channel mixed signal Application Specific Integrated Circuit (ASIC) for Silicon Photo-Multipliers (SiPM) detectors, used in the axial architecture based Time of Flight (ToF) Brain-PET scanners, readout. The current pulses obtained at the output of SiPM arrays are transformed into voltages with the help of charge resistances and then passed to the low noise and high bandwidth preamplifier stages. The amplified pulses are simultaneously passed to the pulse detection modules and the low-pass Sallen-Key filtering stages. The cut-off frequency of the filtering stages is selected as 80 MHz. The denoised pulses are conveyed to the discrete times delay lines (DLs). DLs operate at a 200 MHz sampling frequency and are founded on the base of a novel parallel architecture in place of the classical bucket bridge realization. Each detection module sums up the conditioned pulses of the SiPM pair, mutually aligned 180 degrees apart, and compares its mangnitude with a Leading Edge Discriminator (LED). LEDs outputs are employed by the coincidence detection and address encoding module. DLs are parameterized in order to achieve an effective baseline of around 140 ns while properly coping with the processing delays of the pulse detection, the coincidence detection and the address encoding modules. In the case of a coincidence detection, the concerned delayed pulses are selected by piloting two multiplexers with encoded address and are passed to the post processing modules. The selection process avoids the number of false events processing. It improves the sensitivity, processing efficiency and power consumption of the system. The ASIC is implemented on the 0.35 μm BiCMOS technology. The proposed ASIC functionality is verified with post layout simulations. The typical power consumption is respectively 60.4 mW and 4.693 W for a single channel and for the whole ASIC. Results have confirmed the effectiveness of suggested solution for the SiPM detectors signals readout and selection for Brain-PET applications.

Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e− + 1.5 e−/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

A Power-Efficient Mixed-Signal Smart ADC Design With Adaptive Resolution and Variable Sampling Rate for Low-Power Applications

With the rapid development of portable electronics, wearable devices have become widely used to monitor body signals for long-term health care and home care applications. They detect vital signals through physiological sensors and then transmit them to a cloud database for evaluation and monitoring purposes through wireless communication systems. In this paper, a smart analog-to-digital converter (ADC) was realized by a mixed-signal application-specific integrated circuit (ASIC) based on adaptive resolution and lossless compression techniques for electrocardiogram (ECG) signal monitoring. The sampling clock for the ADC can be adaptively selected according to the characteristic of the signals. The lossless encoder consists of trend forecasting and entropy coding modules. The transmission data rate was decreased efficiently by adaptive resolution and lossless compression techniques. The chip aims to meet the low power consumption for the design, because it reduced the signal transmission rate and maintained high-quality ECG signal detection. The proposed mixed-signal ASIC design was realized using a 0.18-μm CMOS process with a total power consumption of 78.8 μW when operating at 1 kHz and a total chip area of 850 × 850 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A low energy ASIC for triple-chamber cardiac pacemakers with contact resistance measurement

A mixed-signal application specific integrated circuit (ASIC) is presented for triple-chamber pacemakers. To save power, a programmable stimulator composed of a 5-bit low-voltage digital-to-analog converter (DAC) and a triple-mode voltage multiplier is introduced to lower the capacitive load of the charge pump, thus reduces the charge pump driving clock frequency to 100Hz leading to significant reduction in dynamic power. According to refractory periods of the heart, a low-power control strategy is adopted in the sensing channel, in which the opamp is turned on by a sensing command and turned off automatically by a valid sensing event to reduce the average power consumption. Contact resistance measurement function based on bidirectional current injection is also integrated in the ASIC to reflect the connection status and pathological status of the patient's heart. The ASIC is fabricated in a 0.35-μm Bipolar-CMOS-DMOS (BCD) process with a chip area of 3.8mm×3.8mm. Measurement results show that the magnitude of the stimulus pulse can be programmed from 0.1 to 7.5V with 0.1-V step. Almost linear heart resistance measuring is achieved in the resistance range of 250–4000Ω. The average current consumption is 4μA under typical pacing algorithms from a 2.8-V power supply.

High speed digital interfacing for a neural data acquisition system

Abstract Diseases like schizophrenia and genetic epilepsy are supposed to be caused by disorders in the early development of the brain. For the further investigation of these relationships a custom designed application specific integrated circuit (ASIC) was developed that is optimized for the recording from neonatal mice [Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. 16 Channel Neural Recording Integrated Circuit with SPI Interface and Error Correction Coding. Proc. 9th BIOSTEC 2016. Biodevices: Rome, Italy, 2016; 1: 263; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. Development of a neural recording mixed signal integrated circuit for biomedical signal acquisition. Biomed Eng Biomed Tech Abstracts 2015; 60(S1): 298–299; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider WH. 16 Channel Neural Recording Mixed Signal ASIC. CDNLive EMEA 2015 Conference Proceedings, 2015.]. To enable the live display of the neural signals a multichannel neural data acquisition system with live display functionality is presented. It implements a high speed data transmission from the ASIC to a computer with a live display functionality. The system has been successfully implemented and was used in a neural recording of a head-fixed mouse.

A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors

This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 $\mu $ m CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.

Single event effect characterization of the mixed-signal ASIC developed for CCD camera in space use

We present the single event effect (SEE) tolerance of a mixed-signal application-specific integrated circuit (ASIC) developed for a charge-coupled device camera onboard a future X-ray astronomical mission. We adopted proton and heavy ion beams at HIMAC/NIRS in Japan. The particles with high linear energy transfer (LET) of 57.9MeVcm2/mg is used to measure the single event latch-up (SEL) tolerance, which results in a sufficiently low cross-section of σSEL<4.2×10−11cm2/(Ion×ASIC). The single event upset (SEU) tolerance is estimated with various kinds of species with wide range of energy. Taking into account that a part of the protons creates recoiled heavy ions that have higher LET than that of the incident protons, we derived the probability of SEU event as a function of LET. Then the SEE event rate in a low-earth orbit is estimated considering a simulation result of LET spectrum. SEL rate is below once per 49years, which satisfies the required latch-up tolerance. The upper limit of the SEU rate is derived to be 1.3×10−3events/s. Although the SEU events cannot be distinguished from the signals of X-ray photons from astronomical objects, the derived SEU rate is below 1.3% of expected non-X-ray background rate of the detector and hence these events should not be a major component of the instrumental background.

A mixed-signal integrated circuit for FM-DCSK modulation

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER =10/sup -3/ for E/sub b//N/sub o/ lower than 28 dB.

Chip-level charged-device modeling and simulation in CMOS integrated circuits

Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-/spl mu/m CMOS technology show high correlation with the measurement data.