Mixed-radix Fast Fourier Transform Research Articles

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log2 N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N2 – point by using synchronous clock tree.

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors

This brief presents a novel conflict-free access scheme for memory-based fast Fourier transform (FFT) processors. It is proved to satisfy the constraints of the mixed-radix, continuous-flow, parallel-processing, and variable-size FFT computations. An address generation unit is also designed and outperforms existing architectures with reduced gate delay and lower hardware complexity.

High-throughput Low-complexity Mixed-radix FFT Processor using a Dual-path Shared Complex Constant Multiplier

This paper presents a high-throughput lowcomplexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix 2 4 /2 3 FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

Simulation of 32-Point Split-Radix Multipath Delay Commutator (SRMDC) based FFT Architecture

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

Modules for Pipelined Mixed Radix FFT Processors

A set of soft IP cores for the Winogradr-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm byrtimes. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.

Generic Mixed-Radix FFT Pruning

Compared with traditional Fast Fourier Transform (FFT) algorithms, FFT pruning is more computationally efficient in those cases where some of the input values are zero and/or some of the output components are not needed. In this letter, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.

Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems

Designing accelerators for the real-time computation of Fast Fourier Transform (FFT) algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) demodulators has always been challenging. We have scaled-up a template-based Coarse-Grain Reconfigurable Array device for faster FFT processing that generates special purpose accelerators based on the user input. Using a basic and a scaled-up version, we have generated a radix-4 and mixed-radix (2, 4) FFT accelerator to process different length and types of algorithms. Our implementation results show that these accelerators satisfy not only the execution time requirements of FFT processing for Single Input Single Output (SISO) wireless standards that are IEEE-802.11 a/g and 3GPP-LTE but also for Multiple Input Multiple Output (MIMO) IEEE-802.11n standard.

Study and Survey about Mixed Radix FFT Processor in MIMO OFDM

The design of a highly configurable continuous flow mixed-radix (CFMR) Fast Fourier Transform (FFT) processor is presented in Multi-Input Multi-Output (MIMO) Orthogonal frequency division multiplexing (OFDM). Multi-Input Multi-Output (MIMO) system has drawn much attention in 4G wireless technologies. Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless transmission. OFDM may be combined with antenna arrays at the transmitter and receiver to increase the diversity gain and enhance the system capacity on time variant and frequency selective channels, resulting in Multi-Input Multi-Output (MIMO) configuration. This paper represent as Mixed radix FFT in MIMO-OFDM system design including channel modeling, space time block code techniques, channel estimation and signal processing algorithms used for performing time and frequency synchronization in MIMO-OFDM system.

A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-24 algorithm and a radix-23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

Application of Mixed-radix FFT Algorithms in Multi-band GNSS Signal Acquisition Engines

Due to their fast operation, Fast Fourier Transform (FFT)-based coarse signal synchronization methods are an attractive option for Global Navigation Satellite System (GNSS) receiver baseband signal processing. However, there are several reasons why the utility of FFT-based methods is dependent on understanding the trade-off between synchronization speed and the required processing power. Firstly, the new signals of the GNSS family, for instance Galileo and GPS modernization, employ longer period Pseudo Random Noise (PRN) codes and higher signal bandwidths, which demand FFTs of large transform lengths. Secondly, to gain an advantage in positioning performance, next generation receivers target multiple GNSS signals, and since each signal has its own code length (and hence a minimum sampling frequency), the receiver should accommodate FFT blocks of varying lengths. This paper discusses the requirements of FFT-based algorithms for such a multiband receiver and analyzes the application of primefactor and mixed-radix FFT algorithms. A novel way of factorizing different transform lengths into smaller transforms and then combining these smaller-point FFTs to compute the larger required FFTs is described. It is shown that the use of the proposed architecture reduces the computational load (or processor cycles) and increases the re-usability of the acquisition search engine to process different signals.

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.

Use of mixed radix FFT in electric power system studies

Radix-2 based fast Fourier transform (FFT) routines have been the main stream FFT that are commonly applied to the measurement and analysis of electric power system data. Because of the rigid sampling rates offered by most of the instrument manufacturers and the mathematical limitation imposed by the algorithm of radix-2 FFT, artificial post sampling data windows have been introduced to improve the utility of the radix-2 FFT. The 60 Hz and the 50 Hz based electrical power system frequencies are incompatible with the radix-2 FFT. There has been an ongoing search to adapt the FFT routine to the special requirements of electric power systems. Advances in the personal computer hardware has opened a new approach to perform the FFT via mixed radix routines. It offers greatly improved flexibility in the selection of a practical data size. This leads to the elimination of the need of the post sampling software windows. It also allows one to relax or eliminate the requirement of anti-aliasing measures for power system harmonic measurements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-Sorting In-Place Fast Fourier Transforms

It has recently been shown that the familiar radix-2 Fast Fourier Transform (FFT) algorithm can be made both self-sorting and in-place—two useful properties which were previously thought to be mutually exclusive. In this paper the procedure is demonstrated and it is shown how it can be extended toradix-3, radix-4, radix-5, and finally to mixed-radix FFTs. These new versions of the FFT algorithm require neither an unscrambling step nor work space. Implementation on vector computers (for the case of multiple transforms) is discussed. Timing experiments on the Cray X-MP demonstrate that these new variants of the FFT run just as fast as older self sorting routines which required work space.

Unscrambling for fast DFT algorithms

Several methods are reviewed for removing the unscrambler in the prime factor algorithms (PFA) and the types of unscrambler necessary for the Cooley-Tukey FFT (fast Fourier transform) are discussed. It is shown that a radix-4, radix-8, radix-16, or any radix-2/sup m/ FFT can be written to give the output in the same bit-reversed order as the radix-2 FFT. This applies to programs which mix radix-8, radix-4, and radix-2 stages to have the high efficiency of radix-8 and radix-4 and the variety of lengths of radix-2. In a more general form, the method will allow a radix-16 to give its output in the same order as as radix-4 FFT. The method can be used with radix-2/sup m/ Harley, cosine, sine, number-theoretic, and special real-data transforms. This result has practical importance because it allows a single software or hardware bit-reverse counter to unscramble the more efficient radix-4, radix-8, and mixed-radix FFTs. >

One-dimensional spectral analysis of aeromagnetic data from Temiscouata area and the western sector of the Gulf of St. Lawrence

1-D spectral analysis is useful to determine the mean depths to buried magnetic Precambrian basement rocks. The average thickness of the sedimentary cover which may contain favourable petroleum reservoirs overlying the basement of the Northern Appalachians of Quebec was determined by this method. Additional information related to structural geology of the basement and the sedimentary cover can also be obtained with this technique. The center of the Temiscouata area is located at longitude 69° W and latitude 47° 45′ N and the one of the Gulf at 67° 45′ W and 49° 05′ N. The aeromagnetic data were digitized from the 1 mile = 1 inch total field contour maps published by EMR. In the digitization process, the magnetic intensities were read on contour lines only. Interpolation at fixed intervals were calculated with the help of a computer program subroutine. The fixed intervals were chosen at 0.25, 0.50 on shore and 1.00 mile offshore in the Gulf of St. Lawrence. The magnetic gradient was removed using the IGRF formula or numerical filters. The least square method was avoided because of the biasing it involves. Additional smoothing was occasionally done. After these different steps were executed, the transformation to obtain the Fourier co-efficients was carried out using an algorithm for computing the Mixed Radix Fast Fourier Transform. Mean depths are then calculated from the energy spectra; this constitutes a statistical approach. The mean depths obtained from the 1-D energy spectrum are comparable within 10–15% with the ones obtained from the 2-D energy spectrum. 1-D spectral analysis of AM data offers some advantages on the 2-D counterpart. Among these, we can mention the eventuality of obtaining mean depths to the basement from the analysis of only a few AM flight lines in a new area and of detailing more accurately structural features of local nature in the basement. Such structural features may be controlling agents in eventual reservoirs within the sedimentary rocks.

Fixed-point fast Fourier transform error analysis

A statistical model for roundoff errors is used to predict the output noise of the two common forms of the fast Fourier transform (FFT) algorithm, the decimations in-time and in-frequency. This paper deals with two's complement arithmetic with either rounding or chopping. The total mean-square errors and the mean-square errors for the individual points are derived for radix-2 FFT's. Results for mixed-radix FFT are also given.