MIS High Electron Mobility Transistor Research Articles

A dual-gate and Γ-type field plate GaN base E-HEMT with high breakdown voltage on simulation investigation

This paper proposes to insert a buried P-type gate (BPT gate) under the channel layer of the recessed MIS-high electron mobility transistor (HEMT) to form a dual-gate HEMT. And through simulation calculation, the device performance is calculated and the working mechanism of the BPT gate is explained in detail. Compared with a conventional AlGaN/AlN/GaN HEMT and a gate-recessed MIS-HEMT, the dual-gate HEMT has a higher breakdown voltage (1126 V) and a larger threshold voltage (1.5 V). The results show that inserting a BPT gate in a gate-recessed MIS-HEMT can increase the threshold voltage and improve the breakdown characteristics. Through the optimization of the device structure, it is found that the combination of the MIS-gate and the Γ-type field plate based on the dual-gate device can obtain a higher breakdown voltage. Its breakdown voltage can reach 3041 V, and the figure of merit is as high as 3.56 GW cm−2. This reveals that the combination of dual-gate and Γ-type field plate has great potential in the manufacture of enhancement-mode and high-voltage power transistors.

6.2 W/Mm and Record 33.8% PAE at 94 GHz From N-Polar GaN Deep Recess MIS-HEMTs With ALD Ru Gates

This letter reports on the W-band power performance of N-polar GaN deep recess MIS-high electron mobility transistors (HEMTs) using a new atomic layer deposition (ALD) ruthenium (Ru) gate metallization process. The deep recess structure is utilized to control the DC-RF dispersion and increase the conductivity in the access regions. The ALD Ru effectively fills the narrow T-gate stems aiding realization of shorter gate lengths with lower gate resistance than in prior work. In this work, the gate length was scaled down to 48 nm, resulting in the demonstration of a record high 8.1-dB linear transducer gain measured at 94 GHz by load pull. This increased gain has enabled a record 33.8% power-added efficiency (PAE) with an associated output power density ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> ) of 6.2 W/mm.

High performance enhancement-mode HEMT with 3DEG to conduct current and 3DHG as back barrier

Abstract A novel enhancement-mode (E-mode) high electron mobility transistor (HEMT) with three-dimensional electron gas (3DEG) and three-dimensional hole gas (3DHG) is presented. It features a GaN-top layer, a positive graded AlGaN barrier layer (GAL), and a negative graded AlGaN back barrier layer (GABL) (wherein the positive/negative doping gradient is defined with respect to the growth direction), with a vertical conduction channel aside a MIS trench gate. The 2DHG is formed at the interface between the GaN-top layer and GAL. The 3DEG and 3DHG are formed due to the polarization induced by linearly grading Aluminum (Al) composition from 0 to xAl in GAL and 0.4 to 0 in GABL, respectively. The source and drain locate at the same side of the MIS trench gate, and the source contacts with the gate. Firstly, 2DHG blocks the electron current conduction path between the source and 3DEG so as to achieve E-mode. Secondly, the high-sheet density 3DEG in GAL greatly increases the on-state current. Thirdly, the leakage current effectively is reduced by the 3DHG in GABL, improving the breakdown voltage. Fourthly, a high breakdown voltage (BV) is obtained because the polarization junction formed by the polarization charges in GAL and GABL improves the electric field distribution in the drift region. The BV of the proposed HEMT increases to 1080 V from 47 V of the conventional MIS HEMT at the same length of the drift region, and specific on-resistance (Ron,sp) decreases to 0.29 mΩ cm2 from 0.64 mΩ cm2 in simulation.

Performance and V TH Stability in E-Mode GaN Fully Recessed MIS-FETs and Partially Recessed MIS-HEMTs With LPCVD-SiN x /PECVD-SiN x Gate Dielectric Stack

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiN x /PECVD-SiN x ) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance ( ${R}_{ \mathrm{ON}}$ ), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel–Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Reliability Analysis of LPCVD SiN Gate Dielectric for AlGaN/GaN MIS-HEMTs

In this paper, we investigate Low Pressure Chemical Vapor Deposition (LPCVD) SiN as a gate isolation material for AlGaN/gallium nitride (GaN) MIS-high electron mobility transistor power transistors. We compared the dielectric failure by forward-biased constant-current stress time-dependent dielectric breakdown measurements and statistical Weibull analysis. Several 4” AlGaN/GaN-on-Si wafers have been processed with different gate isolations and processes. Our investigation includes the dependence of the dielectric breakdown on the process flow (influence of dry etch), the thickness of the dielectric (12–20 nm), the area scaling, and the gate electrode, where we also consider the recently presented poly-silicon electrode. Additionally, we show the influence of the current density through the gate on the charge-to-breakdown characteristics as well as the influence of the temperature on the breakdown behavior. Using the poly-silicon electrode and 20 nm LPCVD SiN as gate isolation, we achieved a charge-to-breakdown of ${Q}_{\text {BD, 10}~\text {mA}/\text {cm}^{2}} ={3.7} ~ \text {kC}/\text {cm}^{{2}}$ at $\text {T} = {130} {^{\circ }}\text {C}$ for ${j} = {10} ~ \text {mA}/\text {cm}^{{2}}$ . A 20-years lifetime (100 ppm, $\text {T} = {130} {^{\circ }}\text {C}$ ) extrapolation for a scaled area of ${0.2} ~ \text {mm}^{{2}}$ ( $\buildrel \wedge \over = {W}_{G} = {100} ~ \text {mm}$ ) leads to a positive gate voltage of ${V}_{\text {G}} = {9.4} ~ \text {V}$ .

Suppression of Current Collapse in Enhancement Mode GaN-Based HEMTs Using an AlGaN/GaN/AlGaN Double Heterostructure

Current collapse is a phenomenon that increases the channel resistance during the switching process when the high gate and drain voltages are applied. The effect can be found from GaN-based high-electron mobility transistors (HEMTs) and is an obstacle for their applications to power electronics. There have been numerous reports on suppressing current collapse using semiconductor process technologies. In this paper, an enhancement mode (E-mode) AlGaN/GaN/AlGaN double heterostructure was proposed. The current collapse phenomena were studied on devices of E-mode MIS and Schottky gate HEMTs. The results indicate the suppression of current collapse for devices with double heterostructure.

Study of Interface Traps in AlGaN/GaN MISHEMTs Using LPCVD SiN&lt;italic&gt;x&lt;/italic&gt;as Gate Dielectric

Interface trapping is one of the most notorious effects that limit device performance in GaN-based MIS high electron mobility transistors (MISHEMTs). In this paper, we present a comprehensive study on interface traps in AlGaN/GaN MISHEMTs using low pressure chemical vapor deposition SiNx as gate dielectric. We combined the trapping analysis in MIS diodes and actual MISHEMTs to estimate the interface trap state densities ( $\text{D}_{\mathrm {it}})$ and their distributions in the device, and to investigate their influence on device electrical properties. Two types of interface traps with different emission time constants, designated as “slow” and “fast” traps, were identified and characterized by means of pulse-mode current-voltage measurements and a frequency dependent conductance method. It was found that “fast” traps located in the device access region could be effectively restrained by passivation using plasma enhanced chemical vapor deposition SiNx. However, “slow” traps, no matter whether located beneath the metal gate or in the access region, were less influenced by passivation. Due to the strong interference of traps in the access region, $\text{D}_{\mathrm {it}}$ extraction using the conventional conductance method was not accurate for the lateral GaN-based MIS diodes. A modified small-signal equivalent circuit that includes the impedance of traps in the access region is proposed. Proper passivation for the device access region is essential when using the conductance method for GaN-based MIS devices.

High-k/GaN interface engineering toward AlGaN/GaN MIS-HEMT with improved Vth stability

Metal–insulator–semiconductor (MIS) capacitor structures were fabricated on AlGaN/GaN two-dimensional electron gas heterostructure material in order to investigate important aspects of the gate module of a corresponding MIS-high electron mobility transistor device. The process sequence started with an initial wet chemical surface treatment of the as-grown semiconductor material followed by an atomic layer deposition of Al2O3 (high-k first). The electrical analysis focused on the gate leakage current as well as on the shift of the threshold voltage (Vth) upon bias stress in the off- and the on-state regions. The high-k first samples showed much better Vth stability compared to lithographically processed samples, in which the high-k deposition was performed after ohmic contact formation and just before the gate electrode metallization. These results reflect a superior quality of the high-k/GaN interface for the processed structures according to the high-k first approach.

Groove-type channel enhancement-mode AlGaN/GaN MIS HEMT with combined polar and nonpolar AlGaN/GaN heterostructures**Project supported by the National Science and Technology Major Project, China (Grant No. 2013ZX02308-002) and the National Natural Science Foundation of China (Grant Nos. 11435010, 61474086, and 61404099).

A novel groove-type channel enhancement-mode AlGaN/GaN MIS high electron mobility transistor (GTCE-HEMT) with a combined polar and nonpolar AlGaN/GaN heterostucture is presented. The device simulation shows a threshold voltage of 1.24 V, peak transconductance of 182 mS/mm, and subthreshold slope of 85 mV/dec, which are obtained by adjusting the device parameters. Interestingly, it is possible to control the threshold voltage accurately without precisely controlling the etching depth in fabrication by adopting this structure. Besides, the breakdown voltage (VB) is significantly increased by 78% in comparison with the value of the conventional MIS-HEMT. Moreover, the fabrication process of the novel device is entirely compatible with that of the conventional depletion-mode (D-mode) polar AlGaN/GaN HEMT. It presents a promising way to realize the switch application and the E/D-mode logic circuits.

Studies on High-Voltage GaN-on-Si MIS-HEMTs Using LPCVD Si3N4as Gate Dielectric and Passivation Layer

This paper investigates the performance of AlGaN/gallium nitride (GaN) MIS high electron mobility transistors (MIS-HEMTs). The gate dielectric layer and the surface passivation layer are formed by the low-pressure chemical vapor deposition (LPCVD) Si3N4. The LPCVD-Si3N4 MIS-HEMTs exhibit a high breakdown voltage (BV) of 1162 V at $I_{\mathrm{ DS}}= 1~\mu \text{A}$ /mm, a low OFF-state leakage of $7.7 \times 10^{-12}$ A/mm, and an excellent ON/OFF-current ratio of $\sim 10^{11}$ . Compared with the static ON-resistance of 2.88 $\text{m}\Omega \cdot \textrm {cm}^{2}$ , the dynamic ON-resistance after high OFF-state drain bias stress at 600 V only increases to 4.89 $\text{m}\Omega \cdot \textrm {cm}^{2}$ . The power device figure of ${\mathrm{ merit}} = \textrm {BV}^{{\vphantom {R^{l}}{2}}}/R_{{{\mathrm{\scriptscriptstyle ON}.{\mathrm{ sp}}}}}$ is calculated to be 469 $\textrm {MW}\cdot \textrm {cm}^{-2}$ . The LPCVD-Si3N4/GaN interface state density is in the range of (1.4–5.3) $\times 10^{{\vphantom {R^{l}}{13}}}$ eV $^{-1}$ cm $^{-2}$ extracted by the conventional conductance method. Finally, the gate insulator degradation of GaN-based MIS-HEMTs is analyzed by time-dependent dielectric breakdown test. The lifetime is extrapolated to 0.01% of failures after ten years at 300 K by fitting the data with a power law to a gate voltage of 10.1 V.

Normally OFF GaN-on-Si MIS-HEMTs Fabricated With LPCVD-SiNx Passivation and High-Temperature Gate Recess

Low-current-collapse normally OFF GaN-on-Si MIS high-electron-mobility transistors (MIS-HEMTs) are fabricated with low-pressure chemical-vapor-deposited SiN x (LPCVD-SiN x ) passivation and high-temperature low-damage gate-recess technique. The high-thermal-stability LPCVD-SiN x enables a passivation-prior-to-ohmic process strategy and effectively suppresses deep states at the passivation/HEMT interface. The fabricated MIS-HEMTs feature a high $V_{\rm {TH}} $ of +0.85 V at the drain current of 1 $\mu $ A/mm and a remarkable ON/OFF current ratio of 1010 while reduced dynamic ON-resistance as compared to plasma-enhanced chemical-vapor-deposited SiO2 passivation. High field-effect channel mobility of 180 cm $^{2}/ \text{V} \cdot \text{s} $ is achieved, leading to a high maximum drain current density of 663 mA/mm.

Electrical properties of GaN-based metal–insulator–semiconductor structures with Al2O3 deposited by atomic layer deposition using water and ozone as the oxygen precursors

Al2O3 deposited by atomic layer deposition (ALD) was used as an insulator in metal–insulator–semiconductor (MIS) structures for GaN-based MIS-devices. As the oxygen precursors for the ALD process, water (H2O), ozone (O3), and both H2O and O3 were used. The chemical characteristics of the ALD-Al2O3 surfaces were investigated by x-ray photoelectron spectroscopy. After fabrication of MIS-diodes and MIS-high-electron-mobility transistors (MIS-HEMTs) with the ALD-Al2O3, their electrical properties were evaluated by current–voltage (I–V) and capacitance–voltage (C–V) measurements. The threshold voltage of the C–V curves for MIS-diodes indicated that the fixed charge in the Al2O3 layer is decreased when using both H2O and O3 as the oxygen precursors. Furthermore, MIS-HEMTs with the H2O + O3-based Al2O3 showed good dc I–V characteristics without post-deposition annealing of the ALD-Al2O3, and the drain leakage current in the off-state region was suppressed by seven orders of magnitude.

Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High- $k$ Gate Dielectrics

This letter presents details of high-performance enhancement-mode GaN MIS high-electron-mobility transistor (MIS-HEMT) devices. Devices with an n-GaN/i-AlN/n-GaN triple cap layer, a recessed-gate structure, and high- k gate dielectrics show high drain current and complete enhancement-mode operation. The maximum drain current and threshold voltage (V th) are 800 mA/mm and +3 V, respectively. These results indicate that a recessed AlGaN/GaN MIS-HEMT with the triple cap could be a promising new technology for future device applications.