Study of Interface Traps in AlGaN/GaN MISHEMTs Using LPCVD SiN<italic>x</italic>as Gate Dielectric

Abstract

Interface trapping is one of the most notorious effects that limit device performance in GaN-based MIS high electron mobility transistors (MISHEMTs). In this paper, we present a comprehensive study on interface traps in AlGaN/GaN MISHEMTs using low pressure chemical vapor deposition SiNx as gate dielectric. We combined the trapping analysis in MIS diodes and actual MISHEMTs to estimate the interface trap state densities ( $\text{D}_{\mathrm {it}})$ and their distributions in the device, and to investigate their influence on device electrical properties. Two types of interface traps with different emission time constants, designated as “slow” and “fast” traps, were identified and characterized by means of pulse-mode current-voltage measurements and a frequency dependent conductance method. It was found that “fast” traps located in the device access region could be effectively restrained by passivation using plasma enhanced chemical vapor deposition SiNx. However, “slow” traps, no matter whether located beneath the metal gate or in the access region, were less influenced by passivation. Due to the strong interference of traps in the access region, $\text{D}_{\mathrm {it}}$ extraction using the conventional conductance method was not accurate for the lateral GaN-based MIS diodes. A modified small-signal equivalent circuit that includes the impedance of traps in the access region is proposed. Proper passivation for the device access region is essential when using the conductance method for GaN-based MIS devices.