Minority Carrier Generation Research Articles

Saturation Photo-Voltage Methodology for Semiconductor/Insulator Interface Trap Spectroscopy

The presence of large densities of electrically active defects is still an unsolved issue for future high-mobility/high-k CMOS device technologies. This relates to degraded device performance and reliability. Regrettably, conventional admittance-based characterization techniques often fail when applied to non-Si based devices. Among others, enhanced generation of minority carriers and much longer defect time constants make their results inaccurate. Rather than of seeking to adapt commonly-used techniques, we instead aim at direct measuring the semiconductor surface potential by means of the Saturation surface PhotoVoltage (SPV) technique. This approach allows for a DIT estimation which is not limited by the trap response time or hindered by minority carrier generation. Moreover, the DIT can be estimated over the whole bandgap regardless of sample doping type. We here report several case studies in support of the proposed approach. We will also show that SPV can be applied for the characterization of multi-layered Ge and III-V devices incorporating high-k insulators.

Diffusion current characteristics of defect-limited nBn mid-wave infrared detectors

Mid-wave infrared, nBn detectors remain limited by diffusion current generated in the absorber region even when defect concentrations are elevated. In contrast, defect-limited conventional pn-junction based photodiodes are subject to Shockley-Read-Hall generation in the depletion region and subsequent carrier drift. Ideal nBn-architecture devices would be limited by Auger 1 generation; however, typical nBn detectors exhibit defect-dominated performance associated with Shockley-Read-Hall generation in the quasi-neutral absorbing region. Reverse saturation current density characteristics for defect-limited devices depend on the minority carrier diffusion length, absorbing layer thickness, and the dominant minority carrier generation mechanism. Unlike pn-based photodiodes, changes in nBn dark current due to elevated defect concentrations do not manifest at small biases, thus, the zero bias resistance area product, RoA, is not a useful parameter for characterizing nBn-architecture photodetector performance.

Effect of forming gas annealing on the inversion response and minority carrier generation lifetime of n and p-In0.53Ga0.47As MOS capacitors

In0.53Ga0.47As MOS capacitors with a range of Al2O3 oxide thickness values were examined using multi-frequency capacitance–voltage and conductance–voltage characterization for n and p-type In0.53Ga0.47As epitaxial layers. The samples exhibited a minority carrier response consistent with surface inversion for both n and p-type In0.53Ga0.47As MOS structures. An equality between the peak magnitude of the frequency scaled conductance, G/ω, and the derivative of capacitance with frequency, −ωdC/dω in strong inversion allows estimation of accurate Cox values for the varying thickness MOS devices. Minority carrier generation lifetimes, τg, were extracted from the experimentally measured transition frequencies, ωm, through physics based a.c. simulations. It was observed that τg was reduced following a post-metallization 275°C forming gas anneal treatment over both n and p-In0.53Ga0.47As. This is indicative of an improvement in the In0.53Ga0.47As quality by means of hydrogen passivation of the mid-gap bulk defects responsible for the observed minority carrier response.

Capacitance and Conductance for an MOS System in Inversion, with Oxide Capacitance and Minority Carrier Lifetime Extractions

Experimental observations for the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor (MOS) system in inversion indicate that the measured capacitance (C) and conductance (G or G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), are uniquely related through two functions of the alternating current angular frequency (ω). The peak value of the first function (G/ω) is equal to the peak value of the second function (-dC/dlog <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> (ω) ≡ -ωdC/dω). Moreover, these peak values occur at the same angular frequency (ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), that is, the transition frequency. The experimental observations are confirmed by physics-based simulations, and applying the equivalent circuit model for the MOS system in inversion, the functional relationship is also demonstrated mathematically and shown to be generally true for any MOS system in inversion. The functional relationship permits the discrimination between high interface state densities and genuine surface inversion. The two function peak values are found to be equal to C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(2(C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> + C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )) where C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is the oxide capacitance per unit area and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> is the semiconductor depletion capacitance in inversion. The equal peak values of the functions, and their observed symmetry relation about ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> on a logarithmic ω plot, opens a new route to experimentally determining C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> . Finally, knowing ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> permits the extraction of the minority carrier generation lifetime in the bulk of the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As layer.

Modeling Illumination Effects on n- and p-Type InGaAs MOS at Room and Low Temperatures

InGaAs MOS C-V and G-V characteristics are measured under illumination to identify regions of strong minority carrier response related to surface inversion. For the MOS structure with n-type substrate biased in inversion, a high density of surface states in the proximity of the valence band edge is present that masks the response of light generated minority carriers at room temperature. Much stronger effect of illumination is observed at low temperature where the surface-state response is suppressed due to carrier freeze out. On the other hand, for the MOS structure with p-type substrate, strong minority carrier response under illumination is readily observed in inversion even at room temperature, reflecting that the density of surface states near the edge of conduction band is negligible. All the data can be explained in the framework of small-signal equivalent circuit, by modeling the minority carrier generation with a light-dependent conductance plugged in between the conduction band and the valence band. The model is validated against the measured MOS conductance with and without light in inversion.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.

High-temperature thermoelectric transport at small scales: thermal generation, transport and recombination of minority carriers.

Thermoelectric transport in semiconductors is usually considered under small thermal gradients and when it is dominated by the role of the majority carriers. Not much is known about effects that arise under the large thermal gradients that can be established in high-temperature, small-scale electronic devices. Here, we report a surprisingly large asymmetry in self-heating of symmetric highly doped silicon microwires with the hottest region shifted along the direction of minority carrier flow. We show that at sufficiently high temperatures and strong thermal gradients (~1 K/nm), energy transport by generation, transport and recombination of minority carriers along these structures becomes very significant and overcomes convective energy transport by majority carriers in the opposite direction. These results are important for high-temperature nanoelectronics such as emerging phase-change memory devices which also employ highly doped semiconducting materials and in which local temperatures reach ~1000 K and thermal gradients reach ~10–100 K/nm.

Capacitance-voltage characterization of interfaces between positive valence band offset dielectrics and wide bandgap semiconductors

A photo-assisted capacitance voltage (C-V) characterization technique for interfaces between positive valence band offset dielectrics (Al2O3, SiO2) and wide bandgap semiconductors is presented. It is shown that the valence band barrier for holes at the interface affects the measurement and a method to extract border trap and interface state density values from the measured C-V curves is suggested. Dielectric-semiconductor interface characterization has been well studied for silicon but the characterization techniques are not transferable to wide bandgap semiconductors, such as GaN and SiC, due to the low minority carrier generation rate. Multiple dielectrics deposited by various techniques have been employed in these devices; but in order to ascertain the most suitable dielectric, an effective characterization technique that works well with dielectrics on wide-bandgap semiconductors is required.

A simple and accurate method for measuring program/erase speed in a memory capacitor structure

With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.

Capacitance characteristics of atomic layer deposited Al2O3/n-GaN MOS structure

The Ni/Au/Al2O3/n-GaN metal-oxide-semiconductor structure with circular transparent electrode has been fabricated by using atomic layer deposition technique. Effects of ultra-violet (UV) light illumination on the capacitance characteristics and deep interface states are analyzed. Physical origin of bias-induced capacitance drop in the accumulation region of some non-ideal devices is explored. Due to the extremely long electron emission time and the extremely slow minority carrier generation rate, a typical deep depletion behavior can be observed in the dark room-temperature capacitance-voltage sweep curve, and the deep-level interface state occupancy above the electron quasi-Fermi level remains unchanged. Under the UV illumination, photo-induced holes will empty the deep interface traps above the electron quasi-Fermi level, and also de-charge the deep donor-like traps in the oxide layer. The anomalous capacitance drop in the accumulation region is attributed to the bias-dependent excessive leakage conductance across the dielectric layer, which might be induced by a charge-to-breakdown process related to electrical traps in the oxide and the inferior interface quality.

Characterization of dark current in Ge-on-Si photodiodes

Ge-on-Si photodiodes were fabricated from germanium films grown using low-pressure chemical vapor deposition. The mechanisms responsible for the dark current in these devices are studied using geometric analysis, temperature-dependent current-voltage characterization, deep level transient spectroscopy, and device modeling. It is found that an important source of leakage current is associated with the surface depletion region, which is impacted by the nature of the fixed charge at the Ge/dielectric interface. This source of leakage especially affects devices with smaller area, on the order of 10 × 10 μm2. Through a post-metallization anneal (PMA), the dark current of these devices can be reduced by ∼1000X. A similar reduction can be obtained by intentionally doping the top of the germanium film p-type. After the PMA, it is found that the dark current density of large devices is ∼1 mA/cm2, due mainly to generation of minority carriers in the depletion region of the device. The effect of reducing the threading dislocation density is also discussed.

Reducing Formation Time of the Inversion Layer by Illumination around a Memory Capacitor

Capacitor structures are often used to evaluate the program and erase characteristics of charge trapping memory devices. Due to thermally generation of a few minority carriers, the operation efficiency of memory devices is underestimated for the weak response to the formation of inversion layer. In this paper, illumination around a memory capacitor is introduced. Experiment results show that illumination reduces the formation time of the inversion layer and thus increase the program/erase efficiency. Thereby, it is more accurate to characterize program/erase transients of memory devices with capacitor structures under illumination.

Creation of Individual Defects at Extremely High Proton Fluences in Carbon Nanotube $p{-}n$ Diodes

We show that carbon nanotubes are robust under high H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ion fluences. We draw this conclusion by analyzing radiation-induced defects in reconfigurable single-walled carbon nanotube p-n diodes with partially suspended nanotubes. Our analysis show that any defects created through radiation is likely the result of interactions between the nanotube and the substrate, whereas the suspended region of the nanotube remains undamaged. In addition, we show that key features in the diode characteristics can be explained by a single radiation-induced defect that enhances the minority carrier generation rate of only one carrier type.

Improved electrical parameters of vacuum annealed Ni/4H-SiC (0 0 0 1) Schottky barrier diode

The reported work has been focused on the improvement of electrical parameters of Schottky diode using vacuum annealing at mild temperature in Ar gas ambient. Nickel Schottky barrier diodes were fabricated on 50 μm epitaxial layer of n-type 4H-SiC (0 0 0 1) substrate. The values of leakage current, Schottky barrier height ( ϕ B ), ideality factor ( η) and density of interface states ( N SS ) were obtained from experimentally measured current–voltage ( I– V) and capacitance–voltage ( C– V) characteristics before and after vacuum annealing treatment. The data revealed that ϕ B , η and reverse leakage current for the as-processed diodes are 1.25 eV, 1.6 and 1.2 nA (at −100 V), respectively, while for vacuum annealed diodes these parameters are 1.36 eV, 1.3 and 900 pA (at same reverse voltage). Improved characteristics have been resulted under the influence of vacuum annealing because of lesser number of minority carrier generation due to incessant reduction of number of available discrete energy levels in the bandgap of 4H-SiC substrate and lesser number of interface states density at Ni/4H-SiC (0 0 0 1) interface.

Atomic layer deposition temperature dependent minority carrier generation in ZrO2/GeO2/Ge capacitors

Low leakage ZrO2 dielectrics with a thickness of 7 nm are grown by means of atomic layer deposition (ALD) on GeO2-passivated Ge substrates. Substrate temperatures during the deposition of ZrO2 are set to 150 and 250 °C, respectively. The influence of the deposition temperature on electrical and structural properties of metal-oxide-semiconductor capacitors is investigated. A significant impact of the ALD temperature on the high frequency capacitance in inversion is demonstrated. The deposition at 250 °C leads to a substantial loss of interfacial GeOx indicated by time-of-flight secondary ion mass spectroscopy. The loss, which gives rise to trap levels near the oxide/Ge interface, shifts the thermal activation energy of minority carrier generation from a full Ge-bandgap energy to midgap energies.

Hybrid optical and electrical reconfigurable logic gates based on silicon on insulator technology

In this paper we present the first measurements of optically reconfigurable and enabled logic gates based upon the original concept of Silicon-On-Insulator Photo-Activated Modulators (SOI-PAM). The inputs of the fabricated logic gates can either be electric (voltage) or photonic while the output is electric. The principle of the switching operation relays on the optically induced voltage redistribution in SOI Metal-Oxide Semiconductor (MOS) structure. Optical generation of free minority carriers under the buried oxide layer of the SOI cuts-off the conductivity of the silicon channel located on the top layer. By using the photonic commands, the operation rate is expected to be faster. In this paper we show the preliminary experimental validation of such logic gates based on devices having dimensions of less than one cubic micron.

Simulation and Measurements of Stray Minority Carrier Protection Structures in CMOS Image Sensors

Recently, the rapid growth of CMOS technology has made it possible to integrate more periphery circuits into a CMOS image sensor. Although these periphery circuits improve image quality, they also lead to the generation of more stray minority carriers. Because the number of stray minority carriers is proportional to the frequency, the affected region increases with increasing operating frequency. Placing an appropriate absorber between the periphery circuits and the pixel has traditionally been accepted as the best solution for this issue. Four protection tactics were simulated in software and verified in a fabricated CMOS image sensor. The imager was fabricated using TSMC 1-poly 6-metal 0.18-μm process technology. On this chip, ten noise sources outside the pixel array were used to verify the effectiveness of the protection tactics in off-array tests, whereas in-pixel noise sources were used in in-pixel tests. To quantify the influence of stray minority carriers in the off-array test, the maximum depth of an affected region (DAR) was measured in a processed binary image. The off-array experimental results revealed that the DAR increased with either an increased operating frequency or a decreased separation between the noise source and the pixel array. The DAR of the affected pixels can be eliminated up to 48.1% and 23.8% by using the N-well and N-diffusion guard rings, respectively. The in-pixel experimental results have shown that the N-diffusion digital pixel implementation reduced the noise by 63.2% while only increasing the area by 10.68%. Detailed information about the effectiveness of different protection tactics in an imager design was collected in this paper. This paper can potentially provide a reference to help imager designers choose an appropriate protection tactic.

A Circuit-Level Substrate Current Model for Smart-Power ICs

This paper presents a new modeling methodology accounting for generation and propagation of minority carriers that can be used directly in circuit-level simulators in order to estimate coupled parasitic currents. The method is based on a new compact model of basic components (p-n junction and resistance) and takes into account minority carriers at the boundary. An equivalent circuit schematic of the substrate is built by identifying these basic elements in the substrate and interconnecting them. Parasitic effects such as bipolar or latch-up effects result from the continuity of minority carriers guaranteed by the components’ models. A structure similar to a half-bridge perturbing sensitive n-wells has been simulated. It is composed by four p-n junctions connected together by their common p-doped sides. The results are in good agreement with those obtained from physical device simulations.

Charge carrier recombination and generation analysis in materials and devices by electron and optical beam microscopy

Electron beam induced current (EBIC) and optical beam induced current (OBIC) methods of scanning microscopy are here described in view of their applications in the analysis of recombination and generation of carriers in devices and materials. These analyses allow to evidence peculiarities in the charge carriers transport and/or failure in devices charge collection, measuring electrical parameters in the micrometer range, such as potential distribution within the sample, diffusion length and surface recombination velocity. This review will illustrate some case studies relevant to devices and material investigations in the two geometrical configurations: normal and planar. Literature results are reviewed in order to show capabilities and effectiveness of these methods in the investigation of the defect electrical activity and resulting localized minority carrier recombination and generation in devices under operating conditions, as well as in native semiconductor materials such as silicon, gallium arsenide and gallium nitride.

Evaluation of GeO desorption behavior in the metalGeO(2)Ge structure and its improvement of the electrical characteristics.

The relation between germanium monoxide (GeO) desorption and either improvement or deterioration in electrical characteristics of metalGeO(2)Ge capacitors fabricated by thermal oxidation has been investigated. In the metalGeO(2)Ge stack, two processes of GeO desorption at different sites and at different temperatures were observed by thermal desorption spectroscopy measurements. The electrical characteristics of as-oxidized metalGeO(2)Ge capacitors shows a large flat-band voltage shift and minority carrier generation due to the GeO desorption from the GeO(2)Ge interface during oxidation of Ge substrates. On the other hand, the electrical properties were drastically improved by a postmetallization annealing at low temperature resulting in a metal catalyzed GeO desorption from the top interface.