Minimum Operating Voltage Research Articles

A wide input voltage range, high power supply rejection low‐dropout regulator with a closed‐loop charge pump for sensor front‐end circuits

SummaryThis paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits, which is fabricated with a 0.18 μm BCD process. A topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS pass transistors is proposed to increase immunity to electromagnetic interference (EMI) capability for automotive applications. Furthermore, a power‐down protection circuit is proposed to maintain the reliability of the system, and a novel implementation of the charge pump unit is presented to improve the influence of the body effect. Detailed derivation regarding the analyses of the simplified small‐signal model of the closed‐loop charge pump, the loop stability, and the PSR at various frequency bands is given. Simulation and measurement results show that the proposed LDO can operate with the input voltage from 5 to 40 V, providing up to 60 mA current drive capability, and its minimum operating voltage is 2.5 V with a 10 mA load capacity. Moreover, results verify that measured PSR is better than −45 dB at 1.5 kHz, and measured PSR is better than −30 dB at 15 MHz. The results confirm that the obtained parameters of line and load regulations are significantly improved to 1.86 mV/V and 1.75 mV/mA, respectively.

On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond

In this paper, we describe several scaling challenges of SRAM consisting of FinFETs and horizontal Gate-All-Around (GAA) Nano-sheet Field-Effect-Transistors (NshFETs), especially investigations related to Design-Technology Co-Optimization (DTCO). Comb-shaped channel FETs (CombFETs), which integrates the advantages of FinFETs and NshFETs were introduced to a six-transistor (6 T) SRAM cell and the corresponding simulations were established. The results show that compared with both FinFETs and NshFETs, CombFETs have larger the effective channel width or higher current at the same footprint and larger room for improving the mobility mismatch between N/P transistors. Moreover, CombFET SRAM showed ∼55% increase in effective channel width, 15% improvement of read static noise margin, ∼25% write speed gain, 88% read speed gain or 20% decrease in the minimum operating voltage (Vmin).

Thermo-electro-optical properties of seamless metallic nanowire networks for transparent conductor applications.

Rapid reaction time, high attainable temperatures, minimum operating voltage, excellent optical transmittance, and tunable sheet resistance are all desirable properties of transparent conductors, which are important thin-film components in numerous electronic devices. A seamless nanowire network (NWN) refers to a structure composed of nanowires that lack interwire contact junctions, resulting in a continuous and uninterrupted network arrangement. This seamless nature leads to unique properties, including high conductivity and surface area-to-volume ratios, which make it a promising candidate for a vast application range in nanotechnology. Here, we have conducted an in-depth computational investigation to study the thermo-electro-optical properties of seamless nanowire networks and understand their geometrical features using in-house computational implementations and a coupled electrothermal model built in COMSOL Multiphysics software. Sheet resistance calculations were performed using Ohm's law combined with Kirchhoff circuit laws for a random resistor network and compared with those obtained employing COMSOL. In this work, aluminium, gold, copper, and silver nanowires are the materials of choice for testing the transparent conduction performance of our systems. We have studied a wide range of tuning parameters, including the network area fraction, the width-to-depth aspect ratio, and the length of the nanowire segments. We obtained corresponding figures of merit (optical transmittance versus sheet resistance) and temperature distributions to provide a complete characterization of the performance of real-world transparent conductors idealized with seamless NWNs. Our analysis accounted for the thermo-electro-optical responses of the NWNs and the inspection of various controlling parameters depending on system design considerations to shed light on how the electrical transport, optical qualities, and thermal management of these systems can be optimized.

Dynamic Response of Power Systems With Real GICs: Impact on Generator Excitation Control

Geomagneticallyinduced current (GIC) studies usually focus on transformer response to dc but seldom analyze generator excitation systems. A GIC is driven by an electric field which is induced by a very low-frequency geomagnetic field. It is widely acceptable to model GICs with dc, mostly suitable for static voltage stability analysis, but this does not adequately characterize a power system's dynamic response. Considering this, we studied a multi-machine power system on an OPAL-RT digital real-time simulator (DRTS)-MATLAB/Simulink system. We used real GIC measurement data from high and mid-latitude regions. Wavelet analysis related the frequency components of the GIC to the power system's response. A dynamic generator model with excitation voltage control modelled the source. Our main finding is that excitation system control contributes to reducing the voltage drop caused by increased var demand in saturated transformers with GICs. Measured GICs revealed non-negligible short-term dynamics affecting bus voltages that are not captured with dc-modelling assumptions, yet they are important for voltage stability analysis. This study implies that excitation control creates a buffer for high GICs to flow without violating the grid codes for minimum operating voltages and this paper demonstrates the optimization of this novel approach.

Risk-averse Volt-VAr management scheme to coordinate distributed energy resources with demand response program

Distributed energy resources (DERs), such as renewable energy sources (RESs) and energy storage systems (ESSs), are inevitable parts of future power grids. However, the high penetration of RESs may cause voltage violation issues in distribution levels. To this end, the application of the Volt-VAr management (VVM) scheme is highlighted. This paper aims to maintain voltage levels within standard ranges with optimal coordination of different resources at minimum operational costs and voltage deviation. In more detail, this article develops a new VVM in distribution networks to effectively coordinate novel smart grid technologies such as PV inverters, time of use demand response program (TOU-DRP), energy storage systems (ESSs) with traditional devices, including on-line tap changer transformer (OLTC) and switchable capacitor banks (SCBs). Because the coordinated VVM is a bi-objective model that minimizes both operating cost and voltage deviation, it is proposed to use the ε-constraint technique to identify optimal Pareto solutions. To handle the uncertainty related to RESs and load demands, a robust technique based on information gap decision theory (IGDT) is also utilized. The formulation is configured as a mixed-integer linear program (MILP) and solved by CPLEX. It was implemented on the 118-bus distribution network under various conditions. The simulation results clearly show that the coordination of DERs and traditional devices has a significant impact on maintaining voltage levels within permissible ranges while minimizing operational costs. A higher degree of uncertainty radius can also be obtained if DRP participates in the VVM scheme.

An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \mu \text{m}$ </tex-math></inline-formula> 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain.

Threshold Voltage Cancellation For Low Input Voltage of 65nm CMOS Rectifier of Energy Harvesting For Implantable Medical Devices in Telemedicine Embedded System

Telemedicine applications run at very low voltages, necessitating the use of a Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has a lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

High Precision Low Input Voltage of 65nm CMOS Rectifier for Energy Harvesting using Threshold Voltage Minimization in Telemedicine Embedded System

Telemedicine applications run at very low input voltages, necessitating the use of Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

A sub-threshold 10T FinFET SRAM cell design for low-power applications

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM.

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

In this paper, a novel low power consumption device based on a dopingless gate-all-around nanowire tunnel field effect transistor (TFET) with negative capacitance (NC) effect is proposed. NC is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, the threshold voltage (V T) and subthreshold swing (SS) are dropped significantly to less than 60 mV/decade. Negative capacitance makes a significant contribution to the device’s performance by lowering the operating voltage for low-power applications. To calculate the optimum bias, the Landau–Khalatnikov (L–K) equation was used. To evaluate the influence of NC, the ferroelectric (FE) material PZT (lead zirconate titanate), which has perovskite properties, was used as a gate insulator. Thus, the gate-all-around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA NC DL NW TFET. PZT has an appropriate polarization rate, high dielectric capacitance, and a high degree of reliability. To achieve an SS lower than 60 mV/decade at lower V T, effective tuning of the FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device. The aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of the dopingless technique to the nanowire-based TFET. The enhancement of the ON-current with an improved steep SS was addressed. With the application of the NC technique, the proposed device showcased an improved 4 µA µm−1 of I ON, and 1012 of current ratio. Additionally, the influence of the variation in FE thickness on the performance parameters is examined. The proposed device structure operates at a minimum operating voltage, making it an ideal choice for low-power voltage applications.

Enabling In-Memory Computations in Non-Volatile SRAM Designs

The rapid growth in development of neural networks has necessitated the requirement of large capacity on-chip SRAM’s for Machine Learning accelerators. This has resulted in SRAM’s occupying significant portion of the die area. Furthermore, due to increased short channel effects in advanced CMOS technology nodes, the Vt of the transistors are increased to reduce the leakage power effectively. Vt increase results in direct increase in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> (minimum operating voltage) of the device. The conventional 6T SRAM with the use of RRAM(R) to store the bitcell storage node values and PTM(S) as a selector device (6T-2R-2S) can help in decoupling V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and Vt requirement with minimum area overhead. Functionalities of 6T-2R-2S bitcell are investigated to present a 2T-2R-2S mode and SRAM-RRAM hybrid mode of operation, further utilized in performing Compute in Memory(CIM). The above functionalities can be presented in a 8T2R bitcell, that makes use of transistor in place of PTM. 2T-2R-2S/2T-2R mode is a fully non-differential mode of operation, leveraging only the NVM portion of the bitcell. Furthermore, SRAM-RRAM hybrid mode is proposed making use of the SRAM read port transistors to perform read operation of the data stored on the RRAM, during standby mode. The architecture study of set-associative cache made of 6T-2R-2S array is also presented. The 2T-2R-2S/2T-2R mode coupled with SRAM-only mode can be efficiently used to perform CIM for dot product and XNOR computation with co-locating the weights and activations stored onto the same bitcell. System level study highlighting energy efficiency and speedup along with the proposed CIM architecture’s analysis on CIFAR-10 dataset is presented. Design sensitivity analysis with respect to PTM and RRAM parameters is discussed for both the bitcells.

Estimation of minimum operating voltage in fully depleted SOI SRAM cells using gamma distribution

The minimum operating voltage (V min) of every cell on a 32 kb fully depleted SOI static random-access memory (SRAM) macro is successfully measured. Competing V min distribution models, which include the gamma and log-normal distributions, are approximated using the generalized gamma distribution. It is found that the V min of the cells follows the gamma distribution. This finding gives a simple method to estimate the worst V min of an SRAM macro by measuring a few samples and performing linear extrapolation from the gamma distribution.

SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

This brief presents SRAM write assist circuit using cell supply voltage self-collapse with bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near-threshold voltage (Vth) region while consuming a minimal write energy. The proposed SC-BCS improves the write-ability by utilizing the cell supply voltage (CVDD) self-collapse and the feedback operation through the detection of write failure. Because the amount of CVDD collapse is regulated automatically depending on the write-ability of the selected cell, the write energy of the proposed SC-BCS is effectively reduced. The proposed SC-BCS can achieve a 5σ write-ability yield with a smaller delay overhead than gate-modulated self-collapse and self-collapse write assists in the near-Vth region. In addition, the proposed SC-BCS consumes the lowest write energy with minimal delay overhead or without any delay overhead compared with the strong-bias transient CVDD collapse and pulsed-pMOS transient CVDD collapse. The measurement result of the test chip fabricated using 65-nm CMOS technology indicates that the proposed SC-BCS can operate without any failure up to 0.36 V consuming write power 12.6 μW/MHz.

Improved Auxiliary Triggering Topology for High-Power Nanosecond Pulse Generators Based on Avalanche Transistors

The avalanche transistor-based Marx circuit has great advantages in generating high-voltage nanosecond pulses. The introduction of auxiliary triggering topology (ATT) can reduce the damage probability of transistors in M × N-stage Marx bank circuits (MBCs). However, as the number of modified stages increases, the output voltage drops significantly, which makes it not achievable to adopt ATT at each stage. The transistors in nonmodified stages still have a certain failure rate when operating at a high repetition rate. Moreover, the previous ATT is only applicable in the negative polarity MBC. In this article, an improved ATT is proposed to solve the above problems. First, its operating principle is analyzed, and the feasibility of its application in both negative and positive MBCs is verified by simulations. Then, the effects of the improved ATT on M × N-stage MBCs are experimentally studied, and the results show that the improved ATT can be used in all stages of MBC without reducing the output voltage. It can also reduce the minimum operating voltage of transistors and widen the regulating range of output voltage. In addition, it can improve the synchronous conduction of parallel-connected transistors. Finally, two nanosecond pulse generators with positive and negative polarity, respectively, are developed and used to drive the atmospheric pressure plasma jet. The amplitude of output voltage can be adjusted in the range of 5-10 kV, measuring at the open end of a coaxial cable with 75 Ω impedance, and the maximum repetition rate is up to 7 kHz.

Architecture and Optimization of 2T (Footprint) SRAM

A 6T-SRAM bitcell with the footprint of only two transistors is demonstrated by stacking four n-type vertical gate-all-around transistors (VFET) on two pFinFETs. The local interconnects are all within the footprint of the two bottom pFinFETs. The bitcell area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.014~\mu \text{m}^{{2}}$ </tex-math></inline-formula> considering the experimentally achievable metal pitch of 52 nm and bottom pFinFETs of 5 nm node. It can be further reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.009~\mu \text{m}^{{2}}$ </tex-math></inline-formula> considering the metal pitch of 30 nm. The minimum operating voltage is analyzed considering the dominant work function variation. The fin height of pFETs and the gate length of nFETs are used to optimize the read/write static noise margin (RSNM/WSNM) for the same bitcell area. The cell ratio is insensitive to pFET fin height and nFET gate length, leading the read stability to be less affected by pFET fin height and nFET gate length as compared to the write stability. The minimum operating voltage is reduced to 0.59 V using pFET fin height of 15 nm and nFET gate length of 20 nm to balance the read/write SNM without assist circuit techniques. The minimum operating voltage can be further improved to 0.56 V by optimizing the threshold voltage of −0.27 and 0.27 V for pFETs and nFETs, respectively. Moreover, using the negative bitline (NBL) technique can provide an additional 320 mV reduction on the write minimum operating voltage.

A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI

This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V.

Saving of Using Electrical Energy of Induction Motor Through Regulations of Minimum Operating Voltage

Many devices use an induction-type electric motor as the prime mover, such as an electric drilling machine, cutting machine, cement mixer/sand, and various kinds of machinery contained in industrial textiles, automotive industry, and others. The use of machines is closely related to the application of electric motors that will essentially consume electricity vary depending upon the size of the motors that. And generally, this equipment always operates at a nominal price of electrical voltage or full voltage of 220 volts for example per phase or 380-volt three-phase. In this condition, when the motor is not fully loaded suppose half of its full load, it would be a waste of electrical energy consumption, especially if the motor is not given mechanical load on its axis. Therefore, this paper gives a little solution in saving electrical energy consumption of the motor. Two important things are studied in this paper regarding the working arrangements, namely the motor on the state of the start and on the state of the running.

Design of a Charge Pump Circuit and System with Input Impedance Modulation for a Flexible-Type Thermoelectric Generator with High-Output Impedance

This paper describes a charge pump system for a flexible thermoelectric generator (TEG). Even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with low- and high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. How the system can be designed is also described in detail. A design demonstration was performed for the TEG with 400 Ω. The fabricated system was also measured with a flexible-type TEG based on carbon nanotubes. Even with an output impedance of 1.4 kΩ, the system converted thermal energy into electric power of 30 μW at 2.5 V to the following sensor ICs.

A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

ABSTRACT This paper presents a single-ended 9T SRAM cell with data-aware write-word-line structure to improve write ability, and a positive feedback sense amplifier (SA) to solve sensing challenge at an ultra-low voltage. The proposed 9T cell is well suited for bit-interleaving architecture in SRAM array. Simulation results indicate that at a 0.5 V supply voltage, the proposed SRAM cell achieves the same read static noise margin (RSNM) as that of conventional 8T SRAM cell, because the read-decoupled read buffer achieves read-disturb-free operation. While at the same supply voltage, its write margin (WM) is 2.68× compared with the 8T SRAM cell. As a result, a lower minimum operation voltage is achieved. Additionally, its leakage power consumption is reduced by 86.1% compared with the 8T SRAM cell in the 40-nm standard CMOS technology, TT corner, 25°C.

A Disc-Type High Speed Rotary Ultrasonic Motor with Internal Contact Teeth

This paper presents a disc-type ultrasonic piezoelectric motor, which is designed for micro flying vehicles. It provides a high output rotation speed under low operating voltage, compared with common piezoelectric devices, by employing a “contact teeth” wave transmission structure. The ultrasonic motor (USM) consists of a trimorph disc stator, with triple internal contact teeth, a shaft and two hemispheric hard-wearing rotors. The operating principle of the USM is based on the superposition of the in-plane B03 vibration mode of the trimorph disc, and the first longitudinal vibration of the contact teeth. An optimization method of the stator structure parameters was proposed and validated by numerical modeling. The diameter and thickness of the stator are 20 mm and 1 mm, respectively. A prototype with the weight of 2 g was made for this experimental test. The optimal frequency of the excitation signal and the preload force are 98.5 kHz and 0.5 N, respectively. The minimum operating voltage was tested under 7.5 V and reached the speed of 225 rpm, and the maximum unloaded rotational speed of the USM reached 5172 rpm when 30 V driving voltage was applied. The maximum lifting force generated by this USM was measured as 46.1 mN, which is 2.35 times bigger than its weight.