Minimum Delay Time Research Articles

An amorphous silicon integrated inverter

Integration of hydrogenated amorphous silicon field effect transistors (a-Si FET's) has been investigated. It is shown that the new inverter which consists of an n-channel enhancement mode driver FET and a p-channel depletion mode load FET has excellent steplike transfer characteristics. With this integrated inverter, a small-signal gain of more than ten was measured and an integrated ring-oscillator of nine-stages operated for the first time. The power delay product and the minimum propagation delay time were about 480 pJ and 110 µs, respectively.

Temperature effects in the double-pulsed CuCl laser

The results of an experimental study of the thermal dependence of laser pulse energy and of the maximum and minimum delay times between the dissociation and pumping discharge pulses are reported. (AIP)

A low-power and high-speed submicron buried-channel MOSFET fabricated on the buried oxide

Submicrometer buried-channel MOSFET's isolated by a buried oxide layer formed by oxygen ion-implantation technology were fabricated and their switching performances were evaluated. An n-channel E/D MOS ring oscillator with 0.5-µm channel devices has achieved a minimum delay time of 139 ps at 3.5-v drain voltage at room temperature and 78.4 ps at 7-V drain voltage at 77 K.

Hepatic glucose production oscillates in synchrony with the islet secretory cycle in fasting rhesus monkeys.

Oscillations in the concentration of plasma glucose were found to reflect large fluctuations in hepatic glucose production. The fluctuations in glucose production were synchronous with fluctuations in the concentration of plasma insulin and glucagon. This synchrony suggests that hepatic pathways are entrained to the islet cycle with a minimal time delay.

Experimental Study of Amorphous Silicon Integrated Circuit

Integration of amorphous silicon field-effect-transistor is investigated. It is shown experimentally that the new inverter circuit which consists of an n-channel enhancement mode driver FET and a p-channel load FET has excellent step-like transfer characteristics. A small-signal gain of more than 10 was obtained. A nine-stage integrated ring-oscillator operated for the first time. The power delay product and the minimum propagation delay time were about 480 pJ and 110 µs, respectively, which agreed well with the analytical results. It is pointed out that power-delay product could be reduced by more than three orders of magnitude.

Rehabilitation following brain damage: some neurophysiological mechanisms. A therapeutic approach based on theories of motor control.

Rehabilitation programmes concerned with functional recovery of patients with central nervous system (CNS) lesions may be in need of developing processes more consistent with prevailing concepts of motor control and of behavioural requirements by the CNS for motor learning. Both central and peripheral factors can play important roles in providing for finely orchestrated and relatively accurate learned motor performance. The relative influence of each of these factors on motor recovery is determined, in part, by the actions observed, i.e. control of body ("mid-line") and/or limb ("peripheral") position, by the interaction between two principal features of the control system, fixation (stability) and motion, by the inherent plasticity of structures, and by the ability of cerebral mechanisms to code, store and recall information with minimal error and time delay. A functional theory for governing spatial and temporal components of motor performance is presented; this is based upon three attributes: (a) attainment of control of fixation and motion of midline (eye-head-trunk) and peripheral structures in developmental order; (b) organization of serial fixation-motion steps in the guidance-manipulation functions of limbs, and (c) provision for coding spatial and temporal information related to both fixation and motion.

Complementary Schottky transistor logic

AbstractA high‐speed logic circuit, which is compatible on a single chip with I2L (integrated injection logic) and high‐voltage analog circuits is proposed. It is well known that the I2L features low power consumption and high packing density, but that its speed is lower than that of other bipolar circuits. On the other hand, high‐speed bipolar logic circuits consume a lot of power and occupy large area on a silicon chip. This paper proposes a new logic circuit which fills the gap in speed and density between the high‐speed bipolar and I2L circuits and reports the results of experiment. The new logic circuit uses a pnp transistor as a load device and a Schottky‐clamped npn transistor as a driver. An experimental circuit fabricated using an analog‐compatible technology showed a minimum delay time of 1.5 ns and a power‐delay product of 0.5 pJ. A counter circuit was operated at a frequency of 52 MHz.

A High-Speed I2L Process/Structure for VLSI

A high-speed I2L gate for VLSI application has been successfully designed, characterized and demonstrated. The high-speed performance has been achieved in an oxide isolated I2L with a buried-base structure by means of a thin epitaxial layer and heavily doped extrinsic base, and characterized by 0.87 ns of minimum delay time at fan-out of 1 and 1.6 ns at fan-out of 3. The I2L characteristics have been superiorly controlled by optimizing the impurity profile with the reduced pressure epitaxy: For example, the deviation of breakdown voltage (BVCEO) is almost 10% and the deviation of delay time is less than 4%. The influence of device structure on the gate speed has been investigated and then the typical performance for the high-speed gate array which allows propagation delay time down to 3.7 ns at 275 µA/gate injection current has been obtained with the use of 3.4 µm design rule, a dual injector structure and the optimized process.

Laser recrystallized polysilicon for high performance I2L

A key process innovation that has the potential to make very significant improvements in the performance of (integrated injection logic) I2L is proposed and demonstrated. The process is based on replacing the p+extrinsic base-n-substrate parasitic diode with an oxide capacitor, This would eliminate injection current losses to the underlying substrate, thus improving the current gain, the minimum propagation delay time, and the speed-power product of the structure. A buried oxide I2L structure of this type may be realized via the use of pulsed or CW laser recrystallization of polysilicon. An interesting feature of the proposed method is that the crystal material over SiO 2 would not be used for the active transistor area, thus relaxing the stringent material requirements of bipolar devices. The polysilicon may be deposited on a p+base patterned thermal oxide by LPCVD or by deposition in a high temperature epitaxial reactor. The realization of such structures is demonstrated here specifically for the case of pulsed laser annealing of polysilicon deposited by either of the above mentioned ways.

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and the upper silicon is abrupt, and the interface charge density is 6.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . The effective carrier mobility calculated from the drain conductance is 750 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 15 V.

Planar normally-off GaAs JFET for high speed logic circuits

Normally-off JFETs with 1.3 μm-long gates were fabricated by selective double ion implantation for the n and n+ regions and selective Zn diffusion for the p-gate area. A JFET with a 10 μm-wide gate had a transconductance of 2 mS in average and a high value of 3 mS. A 15 stage ring oscillator made of resistively loaded DCFLs showed the minimum delay time of 45 ps, the shortest value obtained based on optical lithography. The minimum power-delay product was 3.8 fJ with a delay time of 83 ps.

Influence of raphe nuclei on neuronal transmission from perforant pathway through dentate gyrus.

1. In chronically prepared, freely moving rats, electrical stimulation was applied to the perforant pathway and monosynaptic responses were recorded extracellularly in the ipsilateral dentate gyrus. In some tests a stimulus was also applied to the median raphe nucleus (mr) prior to activating the perforant pathway. Experiments were performed during two behavioral conditions: slow-wave sleep (SWS) and the still, alert state (SAL). Two varieties of evoked responses were recorded: those due to synchronous firing of neuronal action potentials (evoked action potentials or EAPs) and those produced by excitatory synaptic activity (evoked synaptic potentials or ESPs). 2. As reported previously (38), perforant path stimulation elicited EAPs of greater magnitude during SWS than during SAL. The application of a prior stimulus to mr (prestimulation) markedly increased the already elevated EAPs observed during SWS. The EAPs during SAL were unaffected by prestimulation. 3. The minimum delay time (time between mr and perforant path stimuli) at which the augmentation of the EAPs appeared during SWS was approximately 5 ms. The augmentation reached a maximum at delay times of 25-40 ms and was present up to a delay time of 150 ms. 4. As in former experiments (38), ESPs recorded in the molecular layer of the dentate gyrus after perforant path stimulation were found to be greater during SAL than during SWS. Prestimulation of mr had no significant effect on the ESPs at any level of the molecular layer during either SWS or SAL. 5. The perforant path afferent volley was recorded at high gain in the dentate gyrus. Its amplitude was found to be solely dependent on perforant path stimulus intensity and not on behavioral state or the prestimulation of mr. 6. In preparations anesthetized with Chloropent (82% chloral hydrate, 18% pentobarbital; Fort Dodge Laboratories, Fort Dodge, IA), prestimulation was applied at each of a number of loci within the pons and medulla, including mr, As in SWS, prestimulating mr resulted in augmented EAPs with a minimum delay time of 5 ms. Similar augmented responses were observed when stimulation was applied at other raphe nuclei (dorsal raphe, pontis, magnus, and pallidus), but there was no augmentation when stimulation was applied at other brain stem sites. Threshold stimulus intensities for producing augmented EAPs in the raphe nuclei were less than 30 microA. 7. In freely moving animals it was first established that the EAP responses during SWS were markedly greater than during SAL. Midline lesions were then made at the rostrocaudal level of mr. Following the lesions, there was no longer any significant difference in the magnitude of the EAPs recorded during the two behaviors. 8. These findings suggest that tonic influences arising from raphe nuclei during SWS may be involved in the facilitation of neuronal transmission through the dentate gyrus observed during this behavioral state.

Bounds on Selection Networks

We investigate the complexity of network selection by measuring it in terms of $U(t,N)$, the minimum number of comparators needed, and $T(t,N)$, the minimum delay time possible, for networks selecting the smallest t elements from a set of N inputs. New bounds on $U(t,N)$ and $T(t,N)$ are presented. In particular, the asymptotic forms of $U(t,N)$ and $T(t,N)$ are determined for any fixed t.

Design and Application of a Microprocessor PID Predictor Controller

A digital PID predictor controller is designed and implemented in a microprocessor. The general purpose system controller described permits the use of integer arithmetic for efficient operation with minimum throughput delay time. The stability of the system is investigated and a normalized chart for the selection of the control coefficients for a class of applications is developed. The controller has been applied to the control of a manipulator as a design example.

An Advanced PSA Technology for High-Speed Bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double poly-silicon electrodes, the emitter area is reduced to 1/spl mu/m X 3 /spl mu/m and the base junction is reduced to 0.3 /spl mu/m. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.

Performance, temperature behavior, and first-order modeling of ISL

The minimum propagation delay time of integrated Schottky logic (ISL) made in a standard LS process is determined by saturation of the vertical p-n-p clamp transistor. A performance improvement is obtained by increasing the dope of the substrate to prevent this saturation effect. When using 5 /spl mu/m minimum dimensions the minimum propagation delay is then well below 3 ns over the full temperature range from -55 up to 150/spl deg/C chip temperature. It is shown that a vertical p-n-p clamp transistor is essential to obtain a high speed when relaxed design rules are used. Furthermore, it is shown that ISL can be modeled in a relatively simple manner with one n-p-n transistor and one or two p-n-p transistors, depending on the resistivity of the substrate.

High-Speed Enhancement-Mode GaAs MESFET Logic

High-speed enhancement-mode GaAs MESFET Iogic circuits have been fabricated by electron beam lithography. A 15-stage ring oscillator composed of 0.8-mu m gatelength and 40-mu m gatewidth inverters has given a minimum propagation delay time of 77 ps at a power dissipation of 977 mu W. A minimum power-delay product of 1.6 fJ has been obtained with a 20-mu m gatewidth circuit at a propagation delay time of 200 ps. Liquid nitrogen temperature operation has also been performed, and a speed almost twice higher than that at room temperature has been obtained. The minimum propagation delay time was 51 ps, and the associated power dissipation was 1.9 mW.

An optimum design concept for C-MOS basic logic circuits

A simple and sequential design concept for C-MOS basic logic circuits is proposed. A new concept of speed and pattern area product and a method to obtain the minimum delay time for cascade-connected gates can assure an easy way to determine the W/L ratio for each logic circuit. Using these design concept a. comparisons of delay time and power dissipation are made.

High Speed Enhancement-Mode GaAs MESFET Integrated Circuits

Enhancement-mode GaAs MESFET logics fabricated by electron beam lithography have shown high speed and low power dissipation characteristics. A minimum propagation delay time of 77 ps at a power dissipation of 977 µW was obtainsd for a 0.8 µm gate length ring oscillator. A minimum power-delay product was 1.6 fJ at a propagation delay time of 200 ps. Low temperature operation was also performed and higher switching speed was obtained. The minimum propagation delay time was 44 ps and the associated power dissipation was 2.9 mW at liquid nitrogen temperature.